A flexible high throughput multi-ASIP architecture for LDPC and turbo decoding. - Purushotham Murugappa; Rachid Al-Khayat; Amer Baghdadi; Michel Jézéquel (DATE, 2011)

Area and throughput optimized ASIP for multi-standard turbo decoding. - Rachid Al-Khayat; Purushotham Murugappa; Amer Baghdadi; Michel Jézéquel (International Symposium on Rapid System Prototyping, 2011)

FPGA prototyping and performance evaluation of multi-standard Turbo/LDPC Encoding and Decoding. - Purushotham Murugappa; Jean-Noel Bazin; Amer Baghdadi; Michel Jézéquel (RSP, 2012)

Parameterized area-efficient multi-standard turbo decoder. - Purushotham Murugappa; Amer Baghdadi; Michel Jézéquel (DATE, 2013)

Stopping-Free Dynamic Configuration of a Multi-ASIP Turbo Decoder. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Michael Hübner 001; Jean-Philippe Diguet (DSD, 2013)

Optimizations for an efficient reconfiguration of an ASIP-based turbo decoder. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Jean-Philippe Diguet; Jean-Noel Bazin; Michael Hübner 001 (ISCAS, 2013)

A reconfigurable multi-standard ASIP-based turbo decoder for an efficient dynamic reconfiguration in a multi-ASIP context. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Jean-Philippe Diguet; Jean-Noel Bazin; Michael Hübner 001 (ISVLSI, 2013)

An efficient on-chip configuration infrastructure for a flexible multi-ASIP turbo decoder architecture. - Vianney Lapotre; Michael Hübner 001; Guy Gogniat; Purushotham Murugappa; Amer Baghdadi; Jean-Philippe Diguet (ReCoSoC, 2013)

Rapid design and prototyping of a reconfigurable decoder architecture for QC-LDPC codes. - Purushotham Murugappa; Vianney Lapotre; Amer Baghdadi; Michel Jézéquel (RSP, 2013)

A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding. - Vianney Lapotre; Purushotham Murugappa; Guy Gogniat; Amer Baghdadi; Michael Hübner 001; Jean-Philippe Diguet (IEEE Trans. Very Large Scale Integr. Syst., 2016)

A Reconfigurable Architecture for Posit Arithmetic. - Souradip Sarkar; Purushotham Murugappa; Manil Dev Gomony (DSD, 2019)