Global refinement for building block layout. - Ying-Meng Li; Pushan Tang (ICCAD, 1989)

FPART: A Multi-way FPGA Partitioning Procedure Based on the Improved FM Algorithm. - Rongzheng Zhou; Jiarong Tong; Pushan Tang (ASP-DAC, 1998)

An Analytical Delay Model for SRAM-Based FPGA Interconnections. - Feng Zhou; Zhijun Huang; Jiarong Tong; Pushan Tang (ASP-DAC, 1999)

A constraint-based placement refinement method for CMOS analog cell layout. - Xuan Zeng 001; J. Guan; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS (6), 1999)

Parasitic and mismatch modeling for optimal stack generation [in CMOS]. - Xuan Zeng 001; Mingyuan Li; Wenqing Zhao; Pushan Tang; Dian Zhou (ISCAS, 2000)

Relaxation Algorithm of Piecing-Error for Sub-Images. - Li Yueping; Pushan Tang (J. Comput. Sci. Technol., 2001)

Sequential equivalence checking using cuts. - Wei Huang; Pushan Tang; Min Ding 004 (ASP-DAC, 2005)

Integrating advanced reasoning into a SAT solver. - Min Ding 004; Pushan Tang; Dian Zhou (Sci. China Ser. F Inf. Sci., 2005)

Robust Analog Circuit Sizing Using Ellipsoid Method and Affine Arithmetic. - Xuexin Liu; Wai-Shing Luk; Yu Song; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

WCOMP: Waveform Comparison Tool for Mixed-signal Validation Regression in Memory Design. - Peng Zhang; Wai-Shing Luk; Yu Song; Jiarong Tong; Pushan Tang; Xuan Zeng 001 (ASP-DAC, 2007)

Solving SAT problem by heuristic polarity decision-making algorithm. - Ming-e Jing; Dian Zhou; Pushan Tang; Xiaofang Zhou; Hua Zhang 019 (Sci. China Ser. F Inf. Sci., 2007)

Intel LVS logic as a combinational logic paradigm in CNT technology. - Bao Liu; Zhen Cao; Jun Tao 001; Xuan Zeng 001; Pushan Tang; H.-S. Philip Wong (NANOARCH, 2010)