Physics-based Modeling and Simulation of Dual Material Gate(DMG) LDMOS. - Yuehua Dai; Yuan Hu; Qi Liu 010; Daoming Ke; Junning Chen (APCCAS, 2006)

Formation and annihilation of Cu conductive filament in the nonpolar resistive switching Cu/ZrO2: Cu/Pt ReRAM. - Ming Liu 022; Qi Liu 010; Shibing Long; Weihua Guan (ISCAS, 2010)

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. - Xiaowei Han; Qian Jia; Hongbin Sun 001; Longfei Wang; Huaqiang Wu; Yimao Cai; Feng Zhang 014; Yongyi Xie; Fangxu Dong; Xiaoguang Wang 015; Xiaofei Xue; Li Pang; et al. (CICC, 2017)

Flexible cation-based threshold selector for resistive switching memory integration. - Xiaolong Zhao; Rui Wang; Xiangheng Xiao; Congyan Lu; Facai Wu; Rongrong Cao; Changzhong Jiang; Qi Liu 010 (Sci. China Inf. Sci., 2018)

Resistive Switching Devices: Mechanism, Performance and Integration. - Ming Liu 022; Qi Liu 010; Hangbing Lv; Shibing Long (Handbook of Memristor Networks, 2019)

An Asynchronous AER Circuits with Rotation Priority Tree Arbiter for Neuromorphic Hardware with Analog Neuron. - Jinsong Wei; Jilin Zhang; Xumeng Zhang; Zuheng Wu; Chunmeng Dou; Tuo Shi; Hong Chen 002; Qi Liu 010 (ASICON, 2019)

A Reconfigurable RRAM Physically Unclonable Function Utilizing Post-Process Randomness Source With <6×10-6 Native Bit Error Rate. - Yachun Pang; Bin Gao 006; Dong Wu; Shengyu Yi; Qi Liu 010; Wei-Hao Chen; Ting-Wei Chang; Wei-En Lin; Xiaoyu Sun 001; Shimeng Yu; He Qian; Meng-Fan Chang; et al. (ISSCC, 2019)

A Few-Step and Low-Cost Memristor Logic Based on MIG Logic for Frequent-Off Instant-On Circuits in IoT Applications. - Yiming Wang; Yun Li; Haihua Shen; Dongyu Fan; Wei Wang 003; Ling Li 013; Qi Liu 010; Feng Zhang 014; Xinghua Wang; Meng-Fan Chang; Ming Liu 022 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

33.2 A Fully Integrated Analog ReRAM Based 78.4TOPS/W Compute-In-Memory Chip with Fully Parallel MAC Computing. - Qi Liu 010; Bin Gao 006; Peng Yao; Dong Wu; Junren Chen; Yachuan Pang; Wenqiang Zhang; Yan Liao; Cheng-Xin Xue; Wei-Hao Chen; Jianshi Tang; Yu Wang 002; et al. (ISSCC, 2020)

Ion-Gated Transistor: An Enabler for Sensing and Computing Integration. - Xianbao Bu; Han Xu; Dashan Shang; Yue Li; Hangbing Lv; Qi Liu 010 (Adv. Intell. Syst., 2020)

Conditional Uncorrelation and Efficient Non-approximate Subset Selection in Sparse Regression. - Jianji Wang 001; Qi Liu 010; Nanning Zheng 001 (CoRR, 2020)

An ultra-fast and high-precision VCO frequency calibration technique for fractional-N frequency synthesizers. - Qi Liu 010; Yebing Gan; Tianchun Ye 001 (IEICE Electron. Express, 2020)

Design of Multi-core Spiking Neural Network Chip Based on Butterfly Network. - Hao Jiang 024; Jinsong Wei; Ye Li; Jikai Lu; Tuo Shi; Qi Liu 010 (ASICON, 2021)

RRAM-based Analog-Weight Spiking Neural Network Accelerator with in-situ Learning for IoT Applications. - Jikai Lu; Jinsong Wei; Junjie An; Chenggao Zhang; Tuo Shi; Qi Liu 010 (ASICON, 2021)

Sparsity-Aware Clamping Readout Scheme for High Parallelism and Low Power Nonvolatile Computing-in-Memory Based on Resistive Memory. - Linfang Wang; Wang Ye; Junjie An; Chunmeng Dou; Qi Liu 010; Meng-Fan Chang; Ming Liu 022 (ISCAS, 2021)

Energy-Efficient Memristive Euclidean Distance Engine for Brain-Inspired Competitive Learning. - Houji Zhou; Jia Chen; Yinan Wang; Sen Liu 006; Yi Li 049; Qingjiang Li; Qi Liu 010; Zhongrui Wang; Yuhui He; Hui Xu 010; Xiangshui Miao (Adv. Intell. Syst., 2021)

Recent progress of integrated circuits and optoelectronic chips. - Yue Hao 001; Shuiying Xiang; Genquan Han; Jincheng Zhang; Xiaohua Ma 001; Zhangming Zhu; Xingxing Guo; Yahui Zhang; Yanan Han; Ziwei Song; Yan Liu; Ling Yang 003; et al. (Sci. China Inf. Sci., 2021)

Echo state graph neural networks with analogue random resistor arrays. - Shaocong Wang; Yi Li 049; Dingchen Wang; Woyu Zhang; Xi Chen; Danian Dong; Songqi Wang; Xumeng Zhang; Peng Lin; Claudio Gallicchio; Xiaoxin Xu; Qi Liu 010; et al. (CoRR, 2021)

Efficient and Robust Nonvolatile Computing-In-Memory Based on Voltage Division in 2T2R RRAM With Input-Dependent Sensing Control. - Linfang Wang; Wang Ye; Chunmeng Dou; Xin Si; Xiaoxin Xu; Jing Liu 035; Dashan Shang; Jianfeng Gao 005; Feng Zhang 014; Yongpan Liu; Meng-Fan Chang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. - Keji Zhou; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Deyang Chen; Yujie Huang; Ming-e Jing; Jun Han 003; Haidong Tian; Xiankui Xiong; Qi Liu 010; Xiaoyong Xue; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 200M-Query-Vector/s Computing-in-RRAM ADC-less k-Nearest-Neighbor Accelerator with Time-Domain Winner-Takes-All Circuits. - Chen Mu; Yunzhengmao Wang; Jiapei Zheng; Shiwei Liu 002; Keji Zhou; Shan Tang; Chixiao Chen; Qi Liu 010 (AICAS, 2022)

A 11.6μ W Computing-on-Memory-Boundary Keyword Spotting Processor with Joint MFCC-CNN Ternary Quantization. - Xinru Jia; Haozhe Zhu; Yunzheng Wang; Jinshan Zhang 006; Feng Lin; Xiankui Xiong; Dong Xu 015; Chixiao Chen; Qi Liu 010 (ISCAS, 2022)

COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning. - Haozhe Zhu; Bo Jiao; Jinshan Zhang 006; Xinru Jia; Yunzhengmao Wang; Tianchan Guan; Shengcheng Wang; Dimin Niu; Hongzhong Zheng; Chixiao Chen; Mingyu Wang 001; Lihua Zhang; et al. (ISSCC, 2022)

A neuromorphic core based on threshold switching memristor with asynchronous address event representation circuits. - Jinsong Wei; Jilin Zhang; Xumeng Zhang; Zuheng Wu; Rui Wang; Jian Lu; Tuo Shi; Mansun Chan; Qi Liu 010; Hong Chen 002 (Sci. China Inf. Sci., 2022)

A 28 nm 81 Kb 59-95.3 TOPS/W 4T2R ReRAM Computing-in-Memory Accelerator With Voltage-to-Time-to-Digital Based Output. - Keji Zhou; Xinru Jia; Chenyang Zhao 008; Xumeng Zhang; Guangjian Wu; Chen Mu; Haozhe Zhu; Yanting Ding; Chixiao Chen; Xiaoyong Xue; Xiaoyang Zeng; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2022)

High-Speed and Time-Interleaved ADCs Using Additive-Neural-Network-Based Calibration for Nonlinear Amplitude and Phase Distortion. - Danfeng Zhai; Wenning Jiang; Xinru Jia; Jingchao Lan; Mingqiang Guo; Sai-Weng Sin; Fan Ye 001; Qi Liu 010; Junyan Ren; Chixiao Chen (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

Conditional Uncorrelation and Efficient Subset Selection in Sparse Regression. - Jianji Wang 001; Shupei Zhang; Qi Liu 010; Shaoyi Du; Yu-Cheng Guo; Nanning Zheng 001; Fei-Yue Wang 001 (IEEE Trans. Cybern., 2022)

Fast and Reconfigurable Logic Synthesis in Memristor Crossbar Array. - Wei Wang 003; Sen Liu 006; Qingjiang Li; Tuo Shi; Feng Zhang 014; Haijun Liu 003; Nan Li 020; Yongzhou Wang; Yi Sun; Bing Song; Hui Xu 010; Qi Liu 010 (Adv. Intell. Syst., 2022)

Bit-Offsetter: A Bit-serial DNN Accelerator with Weight-offset MAC for Bit-wise Sparsity Exploitation. - Siqi He; Hongyi Zhang; Mengjie Li; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng (AICAS, 2023)

TiPU: A Spatial-Locality-Aware Near-Memory Tile Processing Unit for 3D Point Cloud Neural Network. - Jiapei Zheng; Hao Jiang 024; Xinkai Nie; Zhangcheng Huang 001; Chixiao Chen; Qi Liu 010 (DAC, 2023)

A $2.53 mu mathrm{W}/ text{channel}$ Event-Driven Neural Spike Sorting Processor with Sparsity-Aware Computing-In-Memory Macros. - Hao Jiang 024; Jiapei Zheng; Yunzhengmao Wang; Jinshan Zhang 006; Haozhe Zhu; Liangjian Lyu; Yingping Chen; Chixiao Chen; Qi Liu 010 (ISCAS, 2023)

A Scalable Die-to-Die Interconnect with Replay and Repair Schemes for 2.5D/3D Integration. - Jie Liao; Bo Jiao; Jinshan Zhang 006; Shiwei Liu 002; Hao Jiang 024; Jun Tao 001; Wenning Jiang; Qi Liu 010; Lihua Zhang; Haozhe Zhu; Chixiao Chen (ISCAS, 2023)

A 28nm 53.8TOPS/W 8b Sparse Transformer Accelerator with In-Memory Butterfly Zero Skipper for Unstructured-Pruned NN and CIM-Based Local-Attention-Reusable Engine. - Shiwei Liu 002; Peizhe Li; Jinshan Zhang 006; Yunzhengmao Wang; Haozhe Zhu; Wenning Jiang; Shan Tang; Chixiao Chen; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

A 9Mb HZO-Based Embedded FeRAM with 1012-Cycle Endurance and 5/7ns Read/Write using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. - Jianguo Yang; Qing Luo; Xiaoyong Xue; Haijun Jiang; Qiqiao Wu; Zhongze Han; Yue Cao; Yongkang Han; Chunmeng Dou; Hangbing Lv; Qi Liu 010; Ming Liu 022 (ISSCC, 2023)

ANP-I: A 28nm 1.5pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-O.1 μJ/Sample On-Chip Learning for Edge-AI Applications. - Jilin Zhang; Dexuan Huo; Jian Zhang 020; Chunqi Qian; Qi Liu 010; Liyang Pan; Zhihua Wang 001; Ning Qiao; Kea-Tiong Tang; Hong Chen 002 (ISSCC, 2023)

Resistive memory-based zero-shot liquid state machine for multimodal event data learning. - Ning Lin; Shaocong Wang; Yi Li 049; Bo Wang 153; Shuhui Shi; Yangu He; Woyu Zhang; Yifei Yu; Yue Zhang 011; Xiaojuan Qi 001; Xiaoming Chen 003; Hao Jiang 024; et al. (CoRR, 2023)

Pruning random resistive memory for optimizing analogue AI. - Yi Li 049; Songqi Wang; Yaping Zhao; Shaocong Wang; Woyu Zhang; Yangu He; Ning Lin; Binbin Cui; Xi Chen; Shiming Zhang; Hao Jiang 024; Peng Lin; et al. (CoRR, 2023)

Random resistive memory-based deep extreme point learning machine for unified visual processing. - Shaocong Wang; Yizhao Gao 002; Yi Li 049; Woyu Zhang; Yifei Yu; Bo Wang 153; Ning Lin; Hegan Chen; Yue Zhang 011; Yang Jiang; Dingchen Wang; Jia Chen; et al. (CoRR, 2023)

Echo state graph neural networks with analogue random resistive memory arrays. - Shaocong Wang; Yi Li 049; Dingchen Wang; Woyu Zhang; Xi Chen; Danian Dong; Songqi Wang; Xumeng Zhang; Peng Lin; Claudio Gallicchio; Xiaoxin Xu; Qi Liu 010; et al. (Nat. Mac. Intell., 2023)

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. - Zhiwang Guo; Deyang Chen; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Yixuan Liu; Haidong Tian; Xiankui Xiong; Keji Zhou; Xiaoyong Xue; Qi Liu 010; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 14b 500 MS/s Single-Channel Pipelined-SAR ADC With Reference Ripple Mitigation Techniques and Adaptively Biased Floating Inverter Amplifier. - Wenning Jiang; Yan Zhu 001; Chixiao Chen; Hao Xu 005; Qi Liu 010; Ming Liu 022; Rui Paulo Martins; Chi-Hang Chan (IEEE J. Solid State Circuits, 2023)

A 28-nm RRAM Computing-in-Memory Macro Using Weighted Hybrid 2T1R Cell Array and Reference Subtracting Sense Amplifier for AI Edge Inference. - Wang Ye; Linfang Wang; Zhidao Zhou; Junjie An; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinshan Yue; Hongyang Hu; Xiaoxin Xu; Jianguo Yang; Jing Liu 035; et al. (IEEE J. Solid State Circuits, 2023)

Ultralow-Power Compact Artificial Synapse Based on a Ferroelectric Fin Field-Effect Transistor for Spatiotemporal Information Processing. - Zhaohao Zhang; Guohui Zhan; Weizhuo Gan; Yan Cheng; Xumeng Zhang; Yue Peng; Jianshi Tang; Fan Zhang; Jiali Huo; Gaobo Xu; Qingzhu Zhang; Zhenhua Wu; et al. (Adv. Intell. Syst., 2023)

Multicore Spiking Neuromorphic Chip in 180-nm With ReRAM Synapses and Digital Neurons. - Hao Jiang 024; Jikai Lu; Chenggao Zhang; Shuangzhu Tang; Junjie An; Lingli Cheng; Jian Lu; Jinsong Wei; Keji Zhou; Xumeng Zhang; Tuo Shi; Qi Liu 010 (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

A 32×32 SPAD LiDAR Sensor with In-pixel Spatial-temporal Coincidence and Per-SPAD Pulse Delay for Resolution-lossless Imaging. - Bu Chen; Zhangcheng Huang 001; Jingyi Wang; Hongyang Shang; Hankun Lv; Qi Liu 010; Ming Liu 022 (A-SSCC, 2024)

A Real-Time Optical-Flow-based SLAM FPGA Accelerator with Inter-Frame Similarity Exploitation and Correlation-Guided Mixed-Precision Flow Update. - Mengjie Li; Haozhe Zhu; Yiming Zhang; Siqi He; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (A-SSCC, 2024)

A 28nm 76.25TOPS/W RRAM/SRAM-Collaborative CIM Fine-Tuning Accelerator with RRAM-Endurance/Latency-Aware Weight Allocation for CNN and Transformer. - Chen Mu; Zhirui Huang; Hao Jiang 024; Jie Liao; Bo Jiao; Yuliang Zhou; Haozhe Zhu; Jianguo Yang; Qi Liu 010; Chixiao Chen (A-SSCC, 2024)

A 13b 500MS/s Dual-Residue Pipelined-SAR ADC with One-Way Switching Capacitive Interpolation and Background Offset Calibration. - Wenning Jiang; Yunbin Luo; Peizhe Li; Ji Guo; Chixiao Chen; Qi Liu 010 (CICC, 2024)

A 32×32 Flash LiDAR SPAD Sensor with Up-to-1kfps Motional Target Detection by Threshold-adaptive 2D Dynamic Vision. - Jingyi Wang; Zhangcheng Huang 001; Bu Chen; Hongyang Shang; Jiapei Zheng; Hankun Lv; Chixiao Chen; Qi Liu 010; Ming Liu 022 (CICC, 2024)

CEDAR: Computing-in-pixel Edge-aware Detection and Reconstruction Architecture for High-resolution 3D Imaging. - Bu Chen; Zhangcheng Huang 001; Qi Zheng 004; Weiyi Tang; Jingyi Wang; Hankun Lv; Chixiao Chen; Jianlu Wang; Qi Liu 010 (DAC, 2024)

CAMPER: Exploring the Potential of Content Addressable Memory for 3D Point Cloud Efficient Range Search. - Jiapei Zheng; Lizhou Wu; Yutong Su; Jingyi Wang; Zhangcheng Huang 001; Chixiao Chen; Qi Liu 010 (DAC, 2024)

High-efficient and Comprehensive Modeling of MFIM Ferroelectric Tunnel Junctions for Non-volatile/Volatile Applications. - Yu Li; Hao Jiang 024; Jie Yu 027; Xuanyu Zhao; Xiaodong Wang; Qihan Liu; Yingfen Wei; Qi Liu 010; Ming Liu 022 (IMW, 2024)

A 128×128 CMOS SPAD Receiver for 500Mbps Free Space Optical Communication with Column-wise Decoding and Fast Spot Tracking. - Bu Chen; Zhangcheng Huang 001; Qi Liu 010 (ISCAS, 2024)

A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-Kelvin. - Jiapei Zheng; Xinkai Nie; Zhenghang Zhi; Zhidong Tang; Qi Liu 010; Xufeng Kou; Chixiao Chen (ISOCC, 2024)

34.9 A Flash-SRAM-ADC-Fused Plastic Computing-in-Memory Macro for Learning in Neural Networks in a Standard 14nm FinFET Process. - Linfang Wang; Weizeng Li; Zhidao Zhou; Hanghang Gao; Zhi Li 062; Wang Ye; Hongyang Hu; Jing Liu 035; Jinshan Yue; Jianguo Yang; Qing Luo; Chunmeng Dou; et al. (ISSCC, 2024)

Resistive Memory-based Neural Differential Equation Solver for Score-based Diffusion Model. - Jichang Yang; Hegan Chen; Jia Chen; Songqi Wang; Shaocong Wang; Yifei Yu; Xi Chen; Bo Wang 153; Xinyuan Zhang; Binbin Cui; Yi Li 049; Ning Lin; et al. (CoRR, 2024)

Efficient and accurate neural field reconstruction using resistive memory. - Yifei Yu; Shaocong Wang; Woyu Zhang; Xinyuan Zhang; Xiuzhe Wu; Yangu He; Jichang Yang; Yue Zhang 011; Ning Lin; Bo Wang 153; Xi Chen; Songqi Wang; et al. (CoRR, 2024)

Continuous-Time Digital Twin with Analogue Memristive Neural Ordinary Differential Equation Solver. - Hegan Chen; Jichang Yang; Jia Chen; Songqi Wang; Shaocong Wang; Dingchen Wang; Xinyu Tian; Yifei Yu; Xi Chen; Yinan Lin; Yangu He; Xiaoshan Wu; et al. (CoRR, 2024)

Dynamic neural network with memristive CIM and CAM for 2D and 3D vision. - Yue Zhang 011; Woyu Zhang; Shaocong Wang; Ning Lin; Yifei Yu; Yangu He; Bo Wang 153; Hao Jiang 024; Peng Lin; Xiaoxin Xu; Xiaojuan Qi 001; Zhongrui Wang; et al. (CoRR, 2024)

A 6.4-Gbps 0.41-pJ/b fully-digital die-to-die interconnect PHY for silicon interposer based 2.5D integration. - Yinglin Yang; Yunzhengmao Wang; Tengyue Yi; Chixiao Chen; Qi Liu 010 (Integr., 2024)

A 9-Mb HZO-Based Embedded FeRAM With 10-Cycle Endurance and 5/7-ns Read/Write Using ECC-Assisted Data Refresh and Offset-Canceled Sense Amplifier. - Qiqiao Wu; Yue Cao; Qing Luo; Haijun Jiang; Zhongze Han; Yongkang Han; Chunmeng Dou; Hangbing Lv; Qi Liu 010; Jianguo Yang; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

Write-Verify-Free MLC RRAM Using Nonbinary Encoding for AI Weight Storage at the Edge. - Junjie An; Zhidao Zhou; Linfang Wang; Wang Ye; Weizeng Li; Hanghang Gao; Zhi Li 062; Jinghui Tian; Yan Wang; Hongyang Hu; Jinshan Yue; Lingyan Fan; et al. (IEEE Trans. Very Large Scale Integr. Syst., 2024)

HARDSEA: Hybrid Analog-ReRAM Clustering and Digital-SRAM In-Memory Computing Accelerator for Dynamic Sparse Self-Attention in Transformer. - Shiwei Liu 002; Chen Mu; Hao Jiang 024; Yunzhengmao Wang; Jinshan Zhang 006; Feng Lin; Keji Zhou; Qi Liu 010; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A Scalable Area-Efficient Low-Delay Asynchronous AER Circuits Design for Neuromorphic Chips. - Siyuan Ouyang; Keji Zhou; Hao Jiang 024; Chenyang Li; Jinhao Liang; Fangduo Zhu; Xumeng Zhang; Qi Liu 010 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

ANP-I: A 28-nm 1.5-pJ/SOP Asynchronous Spiking Neural Network Processor Enabling Sub-0.1-μ J/Sample On-Chip Learning for Edge-AI Applications. - Jilin Zhang; Dexuan Huo; Jian Zhang 020; Chunqi Qian; Qi Liu 010; Liyang Pan; Zhihua Wang 001; Ning Qiao; Kea-Tiong Tang; Hong Chen 002 (IEEE J. Solid State Circuits, 2024)

FPIA: Communication-Aware Multi-Chiplet Integration With Field-Programmable Interconnect Fabric on Reusable Silicon Interposer. - Bo Jiao; Lei Xu; Xinyu Yu; Haitao Yang; Haozhe Zhu; Yu Wang; Jundong Zhu; Dexin Wen; Lingli Wang; Jun Tao 001; Chixiao Chen; Yinhe Han 001; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

SLAM-CIM: A Visual SLAM Backend Processor With Dynamic-Range-Driven-Skipping Linear-Solving FP-CIM Macros. - Mengjie Li; Haozhe Zhu; Siqi He; Hongyi Zhang; Jie Liao; Danfeng Zhai; Chixiao Chen; Qi Liu 010; Xiaoyang Zeng; Ninghui Sun; Ming Liu 022 (IEEE J. Solid State Circuits, 2024)

Hi-NeRF: A Multicore NeRF Accelerator With Hierarchical Empty Space Skipping for Edge 3-D Rendering. - Lizhou Wu; Haozhe Zhu; Jiapei Zheng; Mengjie Li; Yinuo Cheng; Qi Liu 010; Xiaoyang Zeng; Chixiao Chen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A PMOS-Based Deep Cryogenic CMOS Temperature Sensor Achieving a Range from 10K to 410K with a Relative Inaccuracy of 0.5% (3σ). - Xingyu Qi; Yingzhe Sha; Xufeng Kou; Xiaoyong Xue; Peng Wang; Zhangcheng Huang 001; Qi Liu 010; Ming Liu 022 (CICC, 2025)

EIGEN: Enabling Efficient 3DIC Interconnect with Heterogeneous Dual-Layer Network-on-Active-Interposer. - Siyao Jia; Bo Jiao; Haozhe Zhu; Chixiao Chen; Qi Liu 010; Ming Liu 022 (HPCA, 2025)

A 0.22 pJ/bit Processing-in-Controller GEMV Macro with Weight Prefetch for Efficient Near-Memory Computing. - Jie Yang; Jiapei Zheng; Siqi He; Lizhou Wu; Chen Mu; Haozhe Zhu; Liyu Lin; Qi Liu 010; Chixiao Chen (ISCAS, 2025)

37.4 SHINSAI: A 586mm2 Reusable Active TSV Interposer with Programmable Interconnect Fabric and 512Mb 3D Underdeck Memory. - Bo Jiao; Haozhe Zhu; Yuman Zeng; Yongjiang Li; Jie Liao; Siyao Jia; Mochen Tian; Zexing Chen; Jundong Zhu; Dexin Wen; Yan Wang; Yu Wang 046; et al. (ISSCC, 2025)

Resistive memory-based zero-shot liquid state machine for multimodal event data learning. - Ning Lin; Shaocong Wang; Yi Li 049; Bo Wang 153; Shuhui Shi; Yangu He; Woyu Zhang; Yifei Yu; Yue Zhang 011; Xinyuan Zhang; Kwunhang Wong; Songqi Wang; et al. (Nat. Comput. Sci., 2025)

Memristive Hodgkin-Huxley Neurons with Diverse Firing Patterns for High-Order Neuromorphic Computing. - Yue Yang; Xumeng Zhang; Pei Chen; Lingli Cheng; Chao Li; Yanting Ding; Qi Liu 010 (Adv. Intell. Syst., 2025)

A Novel Neuromorphic Hardware Using Area-Efficient Chain RRAM-Based Synapses and Compact Neurons With (Anti-) Integration Scheme. - Qiqiao Wu; Honghu Yang; Yixuan Liu; Yue Cao; Yongkang Han; Haijun Jiang; Keji Zhou; Hailan Yi; Jianguo Yang; Qi Liu 010 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)