Qian Chen
Orcid: 0000-0001-6332-2304Affiliations:
- Nanyang Technological University, School of Electrical and Electronic Engineering, Singapore
According to our database1,
Qian Chen
authored at least 11 papers
between 2019 and 2023.
Collaborative distances:
Collaborative distances:
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on orcid.org
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Bibliography
2023
A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS.
IEEE J. Solid State Circuits, 2023
2022
IEEE Access, 2022
2021
Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
2020
A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks.
Proceedings of the 2019 International SoC Design Conference, 2019
A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks.
Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019
A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019