A 16K SRAM-Based Mixed-Signal In-Memory Computing Macro Featuring Voltage-Mode Accumulator and Row-by-Row ADC. - Hyunjoon Kim; Qian Chen 027; Bongjin Kim (A-SSCC, 2019)

A 1-16b Precision Reconfigurable Digital In-Memory Computing Macro Featuring Column-MAC Architecture and Bit-Serial Computation. - Hyunjoon Kim; Qian Chen 027; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (ESSCIRC, 2019)

A Logic Compatible 4T Dual Embedded DRAM Array for In-Memory Computation of Deep Neural Networks. - Taegeun Yoo; Hyunjoon Kim; Qian Chen 027; Tony Tae-Hyoung Kim; Bongjin Kim (ISLPED, 2019)

A Bit-Precision Reconfigurable Digital In-Memory Computing Macro for Energy-Efficient Processing of Artificial Neural Networks. - Hyunjoon Kim; Qian Chen 027; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (ISOCC, 2019)

A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream Length. - Qian Chen 027; Yuqi Su; Hyunjoon Kim; Taegeun Yoo; Tony Tae-Hyoung Kim; Bongjin Kim (DATE, 2020)

A 3GS/s Highly Linear Energy Efficient Constant-Slope Based Voltage-to-Time Converter. - Qian Chen 027; Yuan Liang 004; Bongjin Kim; Chirn Chye Boon (ISCAS, 2020)

Multi-Channel FSK Inter/Intra-Chip Communication by Exploiting Field-Confined Slow-Wave Transmission Line. - Qian Chen 027; Chirn Chye Boon; Xueyong Zhang; Chenyang Li 008; Yuan Liang 004; Zhe Liu 038; Ting Guo (ISCAS, 2020)

A 6bit 1.2GS/s Symmetric Successive Approximation Energy-Efficient Time-to-Digital Converter in 40nm CMOS. - Qian Chen 027; Yuan Liang 004; Chirn Chye Boon (ISCAS, 2020)

Millimetre-Wave and Terahertz Antennas and Directional Coupler Enabled by Wafer-Level Packaging Platform with Interposer. - Yuan Liang 004; Chirn Chye Boon; Qian Chen 027; Yangtao Dong (ISCAS, 2021)

A 0.6 V 4 GS/s -56.4 dB THD Voltage-to-Time Converter in 28 nm CMOS. - Qian Chen 027; Chirn Chye Boon; Yuan Liang 004 (IEEE Access, 2022)

A Single-Channel Voltage-Scalable 8-GS/s 8-b >37.5-dB SNDR Time-Domain ADC With Asynchronous Pipeline Successive Approximation in 28-nm CMOS. - Qian Chen 027; Chirn Chye Boon; Qing Liu 005; Yuan Liang 004 (IEEE J. Solid State Circuits, 2023)