The Last Mile: An Empirical Study of Timing Channels on seL4. - David A. Cock; Qian Ge 001; Toby C. Murray; Gernot Heiser (CCS, 2014)

Last-Level Cache Side-Channel Attacks are Practical. - Fangfei Liu; Yuval Yarom; Qian Ge 001; Gernot Heiser; Ruby B. Lee (IEEE Symposium on Security and Privacy, 2015)

Mapping the Intel Last-Level Cache. - Yuval Yarom; Qian Ge 001; Fangfei Liu; Ruby B. Lee; Gernot Heiser (IACR Cryptol. ePrint Arch., 2015)

CATalyst: Defeating last-level cache side channel attacks in cloud computing. - Fangfei Liu; Qian Ge 001; Yuval Yarom; Frank McKeen; Carlos V. Rozas; Gernot Heiser; Ruby B. Lee (HPCA, 2016)

Do Hardware Cache Flushing Operations Actually Meet Our Expectations? - Qian Ge 001; Yuval Yarom; Gernot Heiser (CoRR, 2016)

No Security Without Time Protection: We Need a New Hardware-Software Contract. - Qian Ge 001; Yuval Yarom; Gernot Heiser (APSys, 2018)

A survey of microarchitectural timing attacks and countermeasures on contemporary hardware. - Qian Ge 001; Yuval Yarom; David A. Cock; Gernot Heiser (J. Cryptogr. Eng., 2018)

Time Protection: The Missing OS Abstraction. - Qian Ge 001; Yuval Yarom; Tom Chothia; Gernot Heiser (EuroSys, 2019)

Principled Elimination of Microarchitectural Timing Channels through Operating-System Enforced Time Protection. - Qian Ge 001 (2019)