The Design of a 28GHz Mixer-Embedded Frequency Shifting PLL in 65nm CMOS with Low In-Band Phase Noise. - Xinlin Geng; Qian Xie 002; Yibo Tian; Yu Duan; Zheng Wang 050 (ISCAS, 2019)

A Novel Step-shaped Gate Tunnel FET with Low Ambipolar Current. - Mingjun Liu; Qian Xie 002; Shuang Xia; Zheng Wang 050 (ISDCS, 2019)

Short-channel effects on the static noise margin of 6T SRAM composed of 2D semiconductor MOSFETs. - Qian Xie 002; Chen Chen; Mingjun Liu; Shuang Xia; Zheng Wang 050 (Sci. China Inf. Sci., 2019)

A Novel Design of Double Gain Boosting Inductor Cascode Amplifier at Near-fmax Frequencies. - Menghu Ni; Qian Xie 002; Fei He; Zheng Wang 050 (ICTA, 2020)

An Analytical Model of Energy Band Considering Drain Doping Effect of TFET With Exponential Barrier. - Qiao He; Qian Xie 002; Meng Zhao; Zixuan Yang; Zheng Wang 050 (ICTA, 2021)

A New Method to Extract Mobility Degradation and Parasitic Series Resistance of Nano-scaled MOSFETs. - Zixuan Yang; Qian Xie 002; Qiao He; Meng Zhao; Zheng Wang 050 (ICTA, 2021)

A 150-170GHz 5-Bit Vector-Modulated Phase Shifter Based on X-type Phase Inverter Technique. - Zhenyi Zhang; Qian Xie 002; Zheng Wang 050 (ICTA, 2021)

An Accurate Analytical Model for Small Signal Behavior of MOSFET in Terahertz Applications. - Meng Zhao; Qian Xie 002; Zixuan Yang; Qiao He; Zheng Wang 050 (ICTA, 2021)

A study on gain boosting techniques of cascode amplifier at near-fmax frequencies based on gain plane approach. - Fei He; Qian Xie 002; Zheng Wang 050 (Microelectron. J., 2021)

A Quadrature Sub-Sampling Phase Detector for Fast-Relocked Sub-Sampling PLL Under External Interference. - Xinlin Geng; Qian Xie 002; Zheng Wang 050 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Optimize the Efficiency of Lossy Matching Network: A Top-Down Splitting Algorithm Based on Generalized Quality-Based Equation. - Fei He; Qian Xie 002; Zheng Wang 050 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

An Analytical Model for doping effect in charge-plasma-based TFET. - Wenbo Li; Qian Xie 002; Zheng Wang 050 (ICTA, 2022)

A 25.8GHz Integer-N PLL With Time-Amplifying Phase-Frequency Detector Achieving 60fsrms Jitter, -252.8dB FoMJ, and Robust Lock Acquisition Performance. - Xinlin Geng; Yibo Tian; Yao Xiao; Zonglin Ye; Qian Xie 002; Zheng Wang 050 (ISSCC, 2022)

A 26GHz Fractional-N Charge-Pump PLL Based on A Dual-DTC-Assisted Time-Amplifying-Phase-Frequency Detector Achieving 37.1fs and 45.6fs rms Jitter for Integer-N and Fractional-N Channels. - Xinlin Geng; Zonglin Ye; Yao Xiao; Qian Xie 002; Zheng Wang 050 (CICC, 2023)

A Compact Frequency Servo SoC with Background Output Power Calibration for Miniaturized Atomic Clocks. - Xinlin Geng; Zonglin Ye; Kailei Wang; Hongyang Zhang; Qian Xie 002; Zheng Wang 050 (ICTA, 2023)

A Study of Collaborative Gain/Noise Optimization for LNAs at Near- Frequencies Based on a Novel Gain-Noise Plane Approach. - Zhongchen Xu; Qian Xie 002; Zheng Wang 050 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Collaborative gain and noise optimization: a design of 150-173-GHz cascode LNA with 22.3 dB gain and 6.92 dB NF based on the gain-noise plane. - Zhongchen Xu; Menghu Ni; Qian Xie 002; Zheng Wang 050 (Sci. China Inf. Sci., 2023)

A novel gain-boosting structure with Z-embedding and parallel pre-embedding network for amplifiers at near-fmax frequencies. - Fei He; Qian Xie 002; Zheng Wang 050 (Int. J. Circuit Theory Appl., 2023)

A 0.0325-mm² 114-to-147-GHz 6-Bit Passive Vector-Modulated Phase Shifter With MN-Embedded Isolated Power Combiner Achieving <3.7° RMS Phase Error in 65-nm CMOS. - Zhenyi Zhang; Maoxuan Yang; Xinlin Geng; Kailei Wang; Qian Xie 002; Zheng Wang 050 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A 6.8-to-14.4GHz Octave-Tuning Fractional-N Charge-Pump PLL with Slide-Dithering-Based Background DTC Nonlinearity Calibration for Near-Integer Fractional Spur Mitigation Achieving 78fs RMS Jitter and -258.6dB $ text{FoM}_{ mathrm{T}}$. - Zonglin Ye; Xinlin Geng; Zhixiang Shi; Hongyang Zhang; Qian Xie 002; Zheng Wang 050 (CICC, 2024)

Analysis and Design of a Novel Gain-Boosting Technique Based on Lossy Series Embedding Network for Near-fmax Embedded Amplifier. - Fei He; Qian Xie 002; Zheng Wang 050 (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Sub-50-fsrms Jitter Fractional-N CPPLL Based on a Dual-DTC-Assisted Time-Amplifying Phase-Frequency Detector With Cascadable DTC Nonlinearity Compensation Algorithm. - Zonglin Ye; Xinlin Geng; Yao Xiao; Qian Xie 002; Zheng Wang 050 (IEEE J. Solid State Circuits, 2024)