A robust reconfigurable logic device based on less configuration memory logic cell. - Qian Zhao 001; Yoshihiro Ichinomiya; Yasuhiro Okamoto; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (FPT, 2010)

A Variable-Grain Logic Cell and Routing Architecture for a Reconfigurable IP Core. - Kazuki Inoue; Qian Zhao 001; Yasuhiro Okamoto; Hiroki Yosho; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (ACM Trans. Reconfigurable Technol. Syst., 2010)

A novel reconfigurable logic device base on 3D stack technology. - Qian Zhao 001; Yusuke Iwai; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (3DIC, 2011)

A Novel Soft Error Detection and Correction Circuit for Embedded Reconfigurable Systems. - Qian Zhao 001; Yoshihiro Ichinomiya; Motoki Amagasaki; Masahiro Iida; Toshinori Sueyoshi (IEEE Embed. Syst. Lett., 2011)

COGRE: A Novel Compact Logic Cell Architecture for Area Minimization. - Masahiro Iida; Motoki Amagasaki; Yasuhiro Okamoto; Qian Zhao 001; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2012)

A novel FPGA design framework with VLSI post-routing performance analysis (abstract only). - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPGA, 2013)

Defect-robust FPGA architectures for intellectual property cores in system LSI. - Motoki Amagasaki; Kazuki Inoue; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An automatic FPGA design and implementation framework. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2013)

An FPGA design and implementation framework combined with commercial VLSI CADs. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ReCoSoC, 2013)

Three-dimensional stacking FPGA architecture using face-to-face integration. - Tetsuro Hamada; Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2013)

FPGA Design Framework Combined with Commercial VLSI CAD. - Qian Zhao 001; Kazuki Inoue; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2013)

A logic cell architecture exploiting the shannon expansion for the reduction of configuration memory. - Qian Zhao 001; Kyosei Yanagida; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPL, 2014)

A novel three-dimensional FPGA architecture with high-speed serial communication links. - Takuya Kajiwara; Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morituro Kuga; Toshinori Sueyoshi (FPT, 2014)

Simple wafer stacking 3D-FPGA architecture. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (ICICDT, 2015)

Architecture exploration of 3D FPGA to minimize internal layer connection. - Motoki Amagasaki; Yuto Takeuchi; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (VLSI-SoC, 2015)

Fault-Tolerant FPGA: Architectures and Design for Programmable Logic Intellectual Property Core in SoC. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2015)

A 3D FPGA Architecture to Realize Simple Die Stacking. - Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2015)

hCODE: An open-source platform for FPGA accelerators. - Qian Zhao 001; Takuya Nakamichi; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2016)

A Study of Heterogeneous Computing Design Method based on Virtualization Technology. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (SIGARCH Comput. Archit. News, 2016)

A Study of FPGA Virtualization and Accelerator Scheduling. - Qian Zhao 001; Masahiro Iida; Toshinori Sueyoshi (ETCD@ASPLOS, 2017)

hCODE 2.0: An open-source toolkit for building efficient FPGA-enabled clouds. - Qian Zhao 001; Hendarmawan; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (FPT, 2017)

Towards Open-HW: A Platform to Design, Share and Deploy FPGA Accelerators in Low Cost. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IPSJ Trans. Syst. LSI Des. Methodol., 2017)

An Adaptable Scheduling for Self-Reconfigurable Objects. - Mahdillah Mahdillah; Shinya Nakayama; Qian Zhao 001; Takaichi Yoshida (CANDAR Workshops, 2018)

Three Dimensional FPGA Architecture with Fewer TSVs. - Motoki Amagasaki; Masato Ikebe; Qian Zhao 001; Masahiro Iida; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2018)

Enabling FPGA-as-a-Service in the Cloud with hCODE Platform. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Morihiro Kuga; Toshinori Sueyoshi (IEICE Trans. Inf. Syst., 2018)

A Resource Reduced Application-Specific FPGA Switch. - Qian Zhao 001; Yoshimasa Ohnishi; Masahiro Iida; Takaichi Yoshida (ARC, 2019)

A Platform-as-a-Service System for FPGA Education and Development. - Qian Zhao 001; Takaichi Yoshida (CompEd, 2019)

Implementation of FPGA Building Platform as a Cloud Service. - Ryota Watanabe; Saika Ura; Qian Zhao 001; Takaichi Yoshida (HEART, 2019)

A Pre-Routing Net Wirelength Prediction Method Using an Optimized Convolutional Neural Network. - Ryota Watanabe; Yuki Katsuda; Qian Zhao 001; Takaichi Yoshida (CANDAR Workshops, 2019)

A Novel SLM-Based Virtual FPGA Overlay Architecture. - Theingi Myint; Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Masato Kiyama (MCSoC, 2019)

A SLM-based overlay architecture for fine-grained virtual FPGA. - Theingi Myint; Motoki Amagasaki; Qian Zhao 001; Masahiro Iida (IEICE Electron. Express, 2019)

Architecture-aware Cost Function for 3D FPGA Placement Using Convolutional Neural Network. - Qian Zhao 001; Motoki Amagasaki; Masahiro Iida; Takaichi Yoshida (CANDAR, 2020)

A Microcode-based Control Unit for Deep Learning Processors. - Qian Zhao 001; Yasuhiro Nakahara; Motoki Amagasaki; Masahiro Iida; Takaichi Yoshida (IPDPS Workshops, 2020)

Attention Mechanism Driven YOLOv3 on FPGA Acceleration for Efficient Vision Based Defect Inspection. - Longzhen Yu; Qian Zhao 001; Zhixian Wang (CSAE, 2021)

Automation of Domain-specific FPGA-IP Generation and Test. - Yuya Nakazato; Motoki Amagasaki; Qian Zhao 001; Masahiro Iida; Morihiro Kuga (HEART, 2021)

A Study of Reconfigurable Switch Architecture for Chiplets Interconnection. - Hui Meng; Qian Zhao 001; Takaichi Yoshida (CANDARW, 2022)

Reconfigurable Neural Network Accelerator and Simulator for Model Implementation. - Yasuhiro Nakahara; Masato Kiyama; Motoki Amagasaki; Qian Zhao 001; Masahiro Iida (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022)

An eFPGA Generation Suite with Customizable Architecture and IDE. - Morihiro Kuga; Qian Zhao 001; Yuya Nakazato; Motoki Amagasaki; Masahiro Iida (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2023)

Harmonia: A Unified Framework for Heterogeneous FPGA Acceleration in the Cloud. - Luyang Li; Heng Pan; Xinchen Wan; Kai Lv; Zilong Wang 007; Qian Zhao 001; Feng Ning; Qingsong Ning; Shideng Zhang; Zhenyu Li 001; Layong Luo; Gaogang Xie (ASPLOS (2), 2025)