Qiang Li

According to our database1, Qiang Li authored at least 65 papers between 2006 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming.
IEEE J. Solid State Circuits, 2021

2020
A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS.
IEEE Trans. Circuits Syst., 2020

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing.
IEEE Trans. Circuits Syst., 2020

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration.
IEEE J. Solid State Circuits, 2020

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors.
IEEE J. Solid State Circuits, 2020

Enhanced User Grouping and Power Allocation for Hybrid mmWave MIMO-NOMA systems.
CoRR, 2020

23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

Flexible User Grouping for MIMO-NOMA Millimeter Wave Communication Systems.
Proceedings of the 2020 IEEE International Conference on Communications, 2020

2019
Mitigating Intended Jamming in mmWave MIMO by Hybrid Beamforming.
IEEE Wirel. Commun. Lett., 2019

Energy Efficiency of Amplify-and-Forward Full-Duplex Relay Channels.
IEEE Wirel. Commun. Lett., 2019

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Efficient Design-for-Test Approach for Networks-on-Chip.
IEEE Trans. Computers, 2019

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $\Delta\Sigma$ -Modulators.
IEEE J. Solid State Circuits, 2019

A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator.
IEEE J. Solid State Circuits, 2019

Machine Learning-based Signal Detection for PMH Signals in Load-modulated MIMO System.
CoRR, 2019

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019

Online Path-Based Test Method for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)<sup>2</sup>/sqrt(MHz) Noise Floor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
A 0.4-V G<sub>m</sub>-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR.
IEEE J. Solid State Circuits, 2018

A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018

PSP LD-Based Low Complexity Detection Algorithm for M-ary CPM Signals.
Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018

A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

GLRAM Algorithm Based Hybrid Precoding for mmWave Multiuser MIMO Systems.
Proceedings of the 10th IEEE Sensor Array and Multichannel Signal Processing Workshop, 2018

Optimizing dynamic mapping techniques for on-line NoC test.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier.
Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017
Minimizing the system impact of router faults by means of reconfiguration and adaptive routing.
Microprocess. Microsystems, 2017

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A low latency fault tolerant transmission mechanism for Network-on-Chip.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Optimization of the amplifier's input-referred noise for high resolution comparators.
Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016
An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency.
IEEE Trans. Circuits Syst. II Express Briefs, 2016

Phase-error cancellation technique for fast-lock phase-locked loop.
IET Circuits Devices Syst., 2016

A wearable ear-EEG recording system based on dry-contact active electrodes.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping.
Proceedings of the Fourth ACM International Workshop on Many-core Embedded Systems, 2016

Optimizing the location of ECC protection in network-on-chip.
Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2016

Fast-settling technique under large electrode offset in integrated biopotential amplifiers.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks.
Int. J. Sens. Networks, 2015

Central span switching structure for SAR ADC with improved linearity and reduced DAC power.
IEICE Electron. Express, 2015

A fast and energy efficient binary-to-pseudo CSD converter.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2014
A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

A digital calibration technique for multi-bit-per-stage pipelined ADC.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy.
Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs.
Proceedings of the ESSCIRC 2014, 2014

2013
Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A fast correlation based background digital calibration for pipelined ADCs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2008
Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency.
IEEE J. Solid State Circuits, 2007

2006
A Differential CMOS T/R Switch for Multistandard Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2006


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