A Differential CMOS T/R Switch for Multistandard Applications. - Yue-Ping Zhang; Qiang Li 021; Wei Fan; Chew Hoe Ang; He Li (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency. - Qiang Li 021; Y. P. Zhang (IEEE J. Solid State Circuits, 2007)

Antenna-in-Package and Transmit-Receive Switch for Single-Chip Radio Transceivers of Differential Architecture. - Yue-Ping Zhang; Jun Jun Wang; Qiang Li 021; Xue Jun Li (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Waveform distortion performance evaluation using practical antennas in deterministic multipath impulse radio channels. - Zhiyong Guo; Y. P. Zhang; Bo Yan; Qiang Li 021; Guangjun Li; Habib F. Rashvand (IET Commun., 2011)

A multi-rate SerDes transceiver for IEEE 1394b applications. - Longfei Wei; Jinyue Ji; Haiqi Liu; Qiang Li 021 (APCCAS, 2012)

A fast correlation based background digital calibration for pipelined ADCs. - Chuan-Ping Yan; Guangjun Li; Qiang Li 021 (APCCAS, 2012)

A 160mV 670nW 8-bit SAR ADC in 0.13μm CMOS. - Xiong Zhou; Qiang Li 021 (CICC, 2012)

A fast-convergence and robust digital calibration algorithm for a 14-bit 200-MS/s hybrid pipelined-SAR ADC. - Shan Qing; Guang-Jun Li; Qiang Li 021 (MWSCAS, 2012)

An Ultrafast Adaptively Biased Capacitorless LDO With Dynamic Charging Control. - Xin Ming; Qiang Li 021; Ze-kun Zhou; Bo Zhang 027 (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 0.5V rate-resolution scalable SAR ADC with 63.7dB SFDR. - Hai Huang; Kun Ao; Zhiyong Guo; Qiang Li 021 (ISCAS, 2013)

A 13-bit 200MS/s PIPELINE ADC in 0.13µm CMOS. - Junfeng Gao; Bo Chen; Guangjun Li; Qiang Li 021 (MWSCAS, 2013)

High performance SAR ADC with offset and noise tolerance. - Junfeng Gao; Guangjun Li; Qiang Li 021 (MWSCAS, 2013)

A 0.25V 97.8fJ/c.-s. 86.5dB SNDR SC ΔΣ modulator in 0.13µm CMOS. - Zhiliang Qiao; Xiong Zhou; Qiang Li 021 (MWSCAS, 2013)

Hardware-efficient parallel structures for linear-phase FIR digital filter. - Jingjing Tian; Guangjun Li; Qiang Li 021 (MWSCAS, 2013)

Blind-LMS based digital background calibration for a 14-Bit 200-MS/s pipelined ADC. - Yajuan He; Bo Chen; Qiang Li 021 (VLSI-SoC, 2013)

A 250mV 77dB DR 10kHz BW SC ΔΣ Modulator Exploiting Subthreshold OTAs. - Zhiliang Qiao; Xiong Zhou; Qiang Li 021 (ESSCIRC, 2014)

A 10-bit 150MS/s SAR ADC with parallel segmented DAC in 65nm CMOS. - Xiaoyang Wang; Qiang Li 021 (ISCAS, 2014)

A 14-bit 100MS/s pipelined A/D converter with 2b interstage redundancy. - Kun Ao; Yajuan He; Liang Li; Yuxin Wang; Qiang Li 021 (ISIC, 2014)

A digital calibration technique for multi-bit-per-stage pipelined ADC. - Yajuan He; Song Wang; Qi Ling; Qiang Li 021 (ISIC, 2014)

A low-power, CT sigma-delta modulator with a 2b/cycle SAR quantizer. - Lishan Lv; Qiang Li 021 (MWSCAS, 2014)

A energy-efficient high speed segmented prequantize and bypass DAC for SAR ADCs. - Xiaoyang Wang; Xiong Zhou; Qiang Li 021 (MWSCAS, 2014)

An 890 mW stacked power amplifier using SiGe HBTs for X-band multifunctional chips. - Chao Liu; Qiang Li 021; Yihu Li; Xiang Li; Haitao Liu; Yong-Zhong Xiong (ESSCIRC, 2015)

A fast and energy efficient binary-to-pseudo CSD converter. - Yajuan He; Ziji Zhang 001; Bin Ma 010; Jinpeng Li; Shaowei Zhen; Ping Luo 005; Qiang Li 021 (ISCAS, 2015)

300mV 50kHz 75.9dB SNDR CT ΔΣ Modulator with Inverter-based Feedforward OTAs. - Lishan Lv; Qiang Li 021 (ISCAS, 2015)

Central span switching structure for SAR ADC with improved linearity and reduced DAC power. - Junfeng Gao; Guangjun Li; Qiang Li 021 (IEICE Electron. Express, 2015)

Energy efficient comparator for successive approximation register ADCs with application to wireless sensor networks. - Shitong Yuan; Hai Huang; Qilian Liang; Qiang Li 021 (Int. J. Sens. Networks, 2015)

Design Considerations of Ultralow-Voltage Self-Calibrated SAR ADC. - Xiaoyang Wang; Hai Huang; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A High-Speed Energy-Efficient Segmented Prequantize and Bypass DAC for SAR ADCs. - Xiaoyang Wang; Xiong Zhou; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

Fast-settling technique under large electrode offset in integrated biopotential amplifiers. - Hailiang Yao; Xiong Zhou; Sanfeng Zhang; Qiang Li 021 (BioCAS, 2016)

Optimizing the location of ECC protection in network-on-chip. - Junshi Wang; Letian Huang; Qiang Li 021; Guangjun Li; Axel Jantsch (CODES+ISSS, 2016)

VisualNoC: A Visualization and Evaluation Environment for Simulation and Mapping. - Junshi Wang; Yang Huang; Masoumeh Ebrahimi; Letian Huang; Qiang Li 021; Axel Jantsch; Guangjun Li (MES@ISCA, 2016)

A wearable ear-EEG recording system based on dry-contact active electrodes. - Xiong Zhou; Qiang Li 021; Soren Kilsgaard; Farshad Moradi; Simon Lind Kappel; Preben Kidmose (VLSI Circuits, 2016)

Phase-error cancellation technique for fast-lock phase-locked loop. - Zhaoming Ding; Haiqi Liu; Qiang Li 021 (IET Circuits Devices Syst., 2016)

An Amplifier-Free Pipeline-SAR ADC Architecture With Enhanced Speed and Energy Efficiency. - Junfeng Gao; Guangjun Li; Letian Huang; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Optimization of the amplifier's input-referred noise for high resolution comparators. - Qichao He; Xiong Zhou; Qiang Li 021 (ASICON, 2017)

A low latency fault tolerant transmission mechanism for Network-on-Chip. - Letian Huang; Xinxin Lin; Junshi Wang; Qiang Li 021 (ISCAS, 2017)

Non-blocking BIST for continuous reliability monitoring of Networks-on-Chip. - Junshi Wang; Letian Huang; Masoumeh Ebrahimi; Qiang Li 021; Guangjun Li; Axel Jantsch (ISCAS, 2017)

Minimizing the system impact of router faults by means of reconfiguration and adaptive routing. - Junshi Wang; Masoumeh Ebrahimi; Letian Huang; Qiang Li 021; Guangjun Li; Axel Jantsch (Microprocess. Microsystems, 2017)

A Voltage Swing Robust Pseudo-Resistor Structure for Biomedical Front-end Amplifier. - Sanfeng Zhang; Xiong Zhou; Qiang Li 021 (APCCAS, 2018)

A lifetime-aware mapping algorithm to extend MTTF of Networks-on-Chip. - Letian Huang; Shuyu Chen; Qiong Wu; Masoumeh Ebrahimi; Junshi Wang; Shuyan Jiang; Qiang Li 021 (ASP-DAC, 2018)

Optimizing dynamic mapping techniques for on-line NoC test. - Shuyan Jiang; Qiong Wu; Shuyu Chen; Junshi Wang; Masoumeh Ebrahimi; Letian Huang; Qiang Li 021 (ASP-DAC, 2018)

Delta-Measurement Low-Power SAR ADC Architecture with Adaptive Threshold-First Switching. - Zhaoming Ding; Xiong Zhou; Qiang Li 021 (ISCAS, 2018)

An Energy-Efficient Approximate DCT for Wireless Capsule Endoscopy Application. - Yan Xing; Ziji Zhang 001; Yiduan Qian; Qiang Li 021; Yajuan He (ISCAS, 2018)

Micro-Architecture Design for Low Overhead Fault Tolerant Network-on-Chip. - Chikun Yuan; Letian Huang; Junshi Wang; Qiang Li 021 (ISCAS, 2018)

Optimal Slope Ranking: An Approximate Computing Approach for Circuit Pruning. - Ziji Zhang 001; Yajuan He; Jin He; Xilin Yi; Qiang Li 021; Bo Zhang 027 (ISCAS, 2018)

A 65nm 4Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3ns and 55.8TOPS/W fully parallel product-sum operation for binary DNN edge processors. - Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xin Si; En-Yu Yang; Xiaoyu Sun 001; Rui Liu 005; Pai-Yu Chen; Qiang Li 021; Shimeng Yu; Meng-Fan Chang (ISSCC, 2018)

A 0.4V 430nA quiescent current NMOS digital LDO with NAND-based analog-assisted loop in 28nm CMOS. - Xiaofei Ma 004; Yan Lu 002; Rui Paulo Martins; Qiang Li 021 (ISSCC, 2018)

A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC. - Haiwen Chen; Xiong Zhot; Qiang Yu; Fan Zhang; Qiang Li 021 (VLSI Circuits, 2018)

A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator. - Zhaoming Ding; Xiong Zhou; Qiang Li 021 (VLSI Circuits, 2018)

A 0.4-V Gm-C Proportional-Integrator-Based Continuous-Time ΔΣ Modulator With 50-kHz BW and 74.4-dB SNDR. - Lishan Lv; Ankesh Jain; Xiong Zhou; Joachim Becker; Qiang Li 021; Maurits Ortmanns (IEEE J. Solid State Circuits, 2018)

A Multi-Slice VCO-based Quantizer for On-Chip Power Supply Noise Analysis Achieving 0.11 (mV)2/sqrt(MHz) Noise Floor. - Pengfei Zhai; Xiong Zhou; Yan Cai 010; Zheng Zhu; Fan Zhang; Zixiao Lin; Qiang Li 021 (A-SSCC, 2019)

A 12-bit 30MS/s SAR ADC with VCO-Based Comparator and Split-and-Recombination Redundancy for Bypass Logic. - Sheng Chang; Xiong Zhou; Zhaoming Ding; Qiang Li 021 (ISCAS, 2019)

A Loss-Compensated 5-Bit Ka-Band Digital Phase Shifter with Low RMS Phase/Gain Error Over Wide Temperature Ranges. - Ruoman Yang; Chao Liu; Xiangyu Zhao; Sheng Chang; Xiong Zhou; Qiang Li 021 (ISCAS, 2019)

Online Path-Based Test Method for Network-on-Chip. - Junkai Zhan; Letian Huang; Junshi Wang; Masoumeh Ebrahimi; Qiang Li 021 (ISCAS, 2019)

A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning. - Xin Si; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; Yen-Cheng Chiu; Wei-Chen Wei; Ssu-Yen Wu; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; et al. (ISSCC, 2019)

A 0.5-1.1-V Adaptive Bypassing SAR ADC Utilizing the Oscillation-Cycle Information of a VCO-Based Comparator. - Zhaoming Ding; Xiong Zhou; Qiang Li 021 (IEEE J. Solid State Circuits, 2019)

Inverter-Based Subthreshold Amplifier Techniques and Their Application in 0.3-V $ Delta Sigma$ -Modulators. - Lishan Lv; Xiong Zhou; Zhiliang Qiao; Qiang Li 021 (IEEE J. Solid State Circuits, 2019)

Efficient Design-for-Test Approach for Networks-on-Chip. - Junshi Wang; Masoumeh Ebrahimi; Letian Huang; Xuan Xie; Qiang Li 021; Guangjun Li; Axel Jantsch (IEEE Trans. Computers, 2019)

A Dual-Split 6T SRAM-Based Computing-in-Memory Unit-Macro With Fully Parallel Product-Sum Operation for Binarized DNN Edge Processors. - Xin Si; Win-San Khwa; Jia-Jing Chen; Jia-Fang Li; Xiaoyu Sun 001; Rui Liu 005; Shimeng Yu; Hiroyuki Yamauchi; Qiang Li 021; Meng-Fan Chang (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Zhixiao Zhang; Syuan-Hao Sie; et al. (ISSCC, 2020)

25.4 A Scalable 20GHz On-Die Power-Supply Noise Analyzer with Compressed Sensing. - Pengfei Zhai; Xiong Zhou; Yan Cai 010; Zheng Zhu; Fan Zhang; Qiang Li 021 (ISSCC, 2020)

23.7 A 130dB CMRR Instrumentation Amplifier with Common-Mode Replication. - Sanfeng Zhang; Chen Gao; Xiong Zhou; Qiang Li 021 (ISSCC, 2020)

A Twin-8T SRAM Computation-in-Memory Unit-Macro for Multibit CNN-Based AI Edge Processors. - Xin Si; Rui Liu 005; Shimeng Yu; Ren-Shuo Liu; Chih-Cheng Hsieh; Kea-Tiong Tang; Qiang Li 021; Meng-Fan Chang; Jia-Jing Chen; Yung-Ning Tu; Wei-Hsing Huang; Jing-Hong Wang; et al. (IEEE J. Solid State Circuits, 2020)

A 14-bit 4-MS/s VCO-Based SAR ADC With Deep Metastability Facilitated Mismatch Calibration. - Zheng Zhu; Xiong Zhou; Yuheng Du; Yao Feng; Qiang Li 021 (IEEE J. Solid State Circuits, 2020)

A Probabilistic Prediction-Based Fixed-Width Booth Multiplier for Approximate Computing. - Yajuan He; Xilin Yi; Ziji Zhang 001; Bin Ma 010; Qiang Li 021 (IEEE Trans. Circuits Syst., 2020)

An NMOS Digital LDO With NAND-Based Analog-Assisted Loop in 28-nm CMOS. - Xiaofei Ma 004; Yan Lu 002; Qiang Li 021; Wing-Hung Ki; Rui Paulo Martins (IEEE Trans. Circuits Syst., 2020)

A Fully Integrated LDO With 50-mV Dropout for Power Efficiency Optimization. - Xiaofei Ma 004; Yan Lu 002; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Low Power Sample-and-Hold Circuit with Improved Dynamic Bias for Pipelined ADC. - Xiaodan Zhou; Zehao Li; Yujie Wang; Xiong Zhou; Shiheng Yang; Jiaxin Liu; Qiang Li 021 (APCCAS, 2021)

A 640×512 30μm Pixel Pitch 1.8mK-NETD 90.1dB-SNR Digital Read-out Integrated Circuit with Fully On-chip Image Algorithm Pixel-Level Calibration. - Yan Zeng; Shiheng Yang; Yueduo Liu; Zehao Li; Wengang Huang; Xiaozong Huang; Xiong Zhou; Jiaxin Liu; Qiang Li 021 (A-SSCC, 2021)

A 9.08 ENOB 10b 400MS/s Subranging SAR ADC with Subsetted CDAC and PDAS in 40nm CMOS. - Qiang Yu; Xiong Zhou; Kefeng Hu; Zijian Huang 004; Haiwen Chen; Xin Si; Jinda Yang; Qiang Li 021 (ESSCIRC, 2021)

A Comparator Speed Enhancement Technique for Near- and Sub-Threshold ADCs. - Bojun Hu; Sanfeng Zhang; Xiong Zhou; Zehao Li; Xiangxin Pan; Zhaoming Ding; Qiang Li 021 (ICECS, 2021)

Teaching Logic and Sequential Cell Characterization in Digital Integrated Circuits. - Yajuan He; Ziji Zhang 001; Xiong Zhou; Qiang Li 021 (ICETT, 2021)

A Low-Power RC Oscillator with Offset and Path Delay Cancellation. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Shiheng Yang; Jiaxin Liu; Xiong Zhou; Qiang Li 021 (ICTA, 2021)

A Ku-Band SiGe Phased-Array Transceiver with 6-Bit Phase and Attenuation Control. - Bojun Hu; Chao Liu; Sanfeng Zhang; Qiang Li 021 (ISCAS, 2021)

A Sampling Speed Enhancement Technique for Near-Threshold SAR ADCs. - Bojun Hu; Sanfeng Zhang; Xiong Zhou; Xiangxin Pan; Zhaoming Ding; Qiang Li 021 (ISCAS, 2021)

A 40nm 1Mb 35.6 TOPS/W MLC NOR-Flash Based Computation-in-Memory Structure for Machine Learning. - Yuxin Zhang; Sitao Zeng; Zhiguo Zhu; Zhaolong Qin; Chen Wang 130; Jingjing Li 001; Sanfeng Zhang; Yajuan He; Chunmeng Dou; Xin Si; Meng-Fan Chang; Qiang Li 021 (ISCAS, 2021)

15.4 A 5.99-to-691.1TOPS/W Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity-Based Optimization and Variable-Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Te Hu; Hao Li; Limei Tang; Yabing Wang; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; Shouyi Yin (ISSCC, 2021)

A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. - Xin Si; Yung-Ning Tu; Wei-Hsing Huang; Jian-Wei Su; Pei-Jung Lu; Jing-Hong Wang; Ta-Wei Liu; Ssu-Yen Wu; Ruhui Liu; Yen-Chi Chou; Yen-Lin Chung; William Shih; et al. (IEEE J. Solid State Circuits, 2021)

An AC-Coupled Instrumentation Amplifier Achieving 110-dB CMRR at 50 Hz With Chopped Pseudoresistors and Successive-Approximation-Based Capacitor Trimming. - Sanfeng Zhang; Xiong Zhou; Chen Gao; Qiang Li 021 (IEEE J. Solid State Circuits, 2021)

Sampling and Comparator Speed-Enhancement Techniques for Near-Threshold SAR ADCs. - Bojun Hu; Sanfeng Zhang; Xiangxin Pan; Xiangyu Zhao; Zhaoming Ding; Xiong Zhou; Shiheng Yang; Qiang Li 021 (IEEE Open J. Circuits Syst., 2021)

ECDR$^{2}$2: Error Corrector and Detector Relocation Router for Network-on-Chip. - Letian Huang; Chikun Yuan; Junshi Wang; Masoumeh Ebrahimi; Xuan Xie; Qiang Li 021 (IEEE Trans. Computers, 2021)

A 600-μm² Ring-VCO-Based Hybrid PLL Using a 30-μW Charge-Sharing Integrator in 28-nm CMOS. - Shiheng Yang; Jun Yin 001; Tailong Xu; Taimo Yi; Pui-In Mak; Qiang Li 021; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 4.2-to-5.6 GHz Transformer-Based PMOS-only Stacked-gm VCO in 28-nm CMOS. - Mingkang Zhang; Zihao Zhu; Yueduo Liu; Zehao Zhang; Rongxin Bao; Jiahui Lin; Haovu Zhuang; Jiaxin Liu; Xiong Zhou; Shiheng Yang; Qiang Li 021 (ICTA, 2022)

Bitwise ELD Compensation in Δ∑ Modulators. - Michael Pietzko; Jonathan Ungethüm; John G. Kauffman; Qiang Li 021; Maurits Ortmanns (ISCAS, 2022)

A 100dB-TCMRR 8-Channel Bio-Potential Front-End with Multi-Channel Common-Mode Replication. - Borui Tan; Sanfeng Zhang; Chen Gao; Xiong Zhou; Qiang Li 021 (ISCAS, 2022)

Maximizing the Inter-Stage Gain in CT 0-X MASH Delta-Sigma-Modulators. - Jonathan Ungethüm; Michael Pietzko; John G. Kauffman; Qiang Li 021; Maurits Ortmanns (ISCAS, 2022)

A 13-bit 1-MS/s SAR ADC With Rotation-Based Mismatch Error Cancellation. - Jing Zhang; Lulu Zhang; Xiong Zhou; Maurits Ortmanns; Qiang Li 021 (ISCAS, 2022)

16- and 64-Point Analog Computing of FFT with Improved Performance and Efficiency. - Jingjing Li 001; Xingchen Chao; Qiang Li 021 (PRIME, 2022)

An On-Chip Power-Supply Noise Analyzer With Compressed Sensing and Enhanced Quantization. - Pengfei Zhai; Zheng Zhu; Xiong Zhou; Yan Cai 010; Fan Zhang; Qiang Li 021 (IEEE J. Solid State Circuits, 2022)

A 130-dB CMRR Instrumentation Amplifier With Common-Mode Replication. - Sanfeng Zhang; Xiong Zhou; Chen Gao; Qiang Li 021 (IEEE J. Solid State Circuits, 2022)

Accurate Performance Evaluation of Jitter-Power FOM for Multiplying Delay-Locked Loop. - Yueduo Liu; Rongxin Bao; Zihao Zhu; Shiheng Yang; Xiong Zhou; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 0.69-Noise-Efficiency-Factor 4 x-Current-Reuse Dynamic Comparator with A Stacking FIA. - Haoyu Zhuang; Nan Sun 001; Yirui Cao; Linzhi Tao; Qiang Li 021 (CICC, 2023)

A 128-GS/s Timing-Robust Sampling Architecture Exploiting Analog FFT. - Xingchen Chao; Qiang Li 021 (ISCAS, 2023)

A Low-Noise and Settling-Enhanced Switched-Capacitor Amplifier With Correlated Level Shifting and Bandwidth Switching. - Feng Tai; Ziqin Nie; Yinhao Wang; Xingchen Chao; Qiang Li 021 (ISCAS, 2023)

Bitwise ELD Compensation under Integrator Nonidealities in ΔΣ Modulators. - Michael Pietzko; Julian Spiess; Jonathan Ungethüm; John G. Kauffman; Qiang Li 021; Maurits Ortmanns (NEWCAS, 2023)

Improved Dynamic Comparator With Adaptive Delay Line for the Latch Conduction and Regenerative Feedback Assisted FIA. - Feng Tai; Qiang Li 021 (NEWCAS, 2023)

On the DC-Settling Process of the Pierce Crystal Oscillator in Start-Up. - Zehao Zhang; Shiheng Yang; Yueduo Liu; Zihao Zhu; Jiahui Lin; Rongxin Bao; Tailong Xu; Zhizhan Yang; Mingkang Zhang; Jiaxin Liu; Xiong Zhou; Jun Yin 001; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

TT@CIM: A Tensor-Train In-Memory-Computing Processor Using Bit-Level-Sparsity Optimization and Variable Precision Quantization. - Ruiqi Guo; Zhiheng Yue; Xin Si; Hao Li; Te Hu; Limei Tang; Yabing Wang; Hao Sun; Leibo Liu; Meng-Fan Chang; Qiang Li 021; Shaojun Wei; et al. (IEEE J. Solid State Circuits, 2023)

A 0.0043-mm2 0.085-μW/MHz Relaxation Oscillator Using Charge-Prestored Asymmetric Swings R-RC Network. - Yuchen Wei; Shiheng Yang; Yueduo Liu; Rongxin Bao; Zihao Zhu; Jiahui Lin; Zehao Zhang; Yong Chen 005; Jun Yin 001; Pui-In Mak; Qiang Li 021 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

131TOPS/W 8b ACIM Exploiting Weight-Embedded Auto-Accumulation and Supporting Symmetric Quantization Networks. - Wei He; Puvi Bai; Hongyang Luo; Zhenghao Jin; Han Wu; Junyi Zhang; Xingchen Chao; Haiqi Liu; Yajuan He; Qiang Li 021 (CICC, 2024)

A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS. - Xiaodan Zhou; Weipeng He; Dongbing Fu; Jianan Wang; Guangbing Chen; Qiang Li 021 (Microelectron. J., 2024)

A Compact Sub-nW/kHz Relaxation Oscillator Using a Negative-Offset Comparator With Chopping and Piecewise Charge-Acceleration in 28-nm CMOS. - Yueduo Liu; Zihao Zhu; Rongxin Bao; Jiahui Lin; Jun Yin 001; Qiang Li 021; Pui-In Mak; Shiheng Yang (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 20 MHz, 98.7 dB-SFDR, Capacitively Degenerated Dynamic Amplifier Without Bias Voltage Calibrations. - Ruofan Zhang; Haoyu Zhuang; Yirui Cao; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 0.8-V Supply, 1.58% 3σ-Accuracy, 1.9-μW Bandgap Reference in 0.13-μm CMOS. - Yirui Cao; Haoyu Zhuang; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Deep Learning Assisted Multiuser MIMO Load Modulated Systems for Enhanced Downlink mmWave Communications. - Ercong Yu; Jinle Zhu; Qiang Li 021; Zi Long Liu 001; Hongyang Chen; Shlomo Shamai Shitz; H. Vincent Poor (IEEE Trans. Wirel. Commun., 2024)

A 0.5-V Voltage Reference Using Simple Common-Source Amplifier With Improved Gain. - Haoyu Zhuang; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Timing-Robust 10b 13GS/s ADC with Analog Fourier Transform Based Frequency Interleaving. - Xingchen Chao; Yunqiang Xu; Qiang Yu; Zheng Zhu; Sanfeng Zhang; Qiang Li 021 (CICC, 2025)

A 0.69-Noise-Efficiency-Factor 55× -Preamp-Gain Dynamic Comparator With a Stacking FIA. - Haoyu Zhuang; Yirui Cao; Linzhi Tao; Qiang Li 021 (IEEE J. Solid State Circuits, 2025)

A High-Accuracy Bandgap Reference With Compact Output Driver. - Haoyu Zhuang; Yizhan Li; Xingyu Wang; Liangchen Huang; Qiang Li 021 (IEEE Trans. Circuits Syst. II Express Briefs, 2025)

Graph-Based Joint Client Clustering and Resource Allocation for Wireless Distributed Learning: A New Hierarchical Federated Learning Framework With Non-IID Data. - Ercong Yu; Shanyun Liu; Qiang Li 021; Hongyang Chen; H. Vincent Poor; Shlomo Shamai (IEEE Trans. Mob. Comput., 2025)