Qiang Liu

Orcid: 0000-0003-1375-0508

Affiliations:
  • Tianjin University, School of Microelectronics, China
  • Imperial College London, Department of Electrical and Electronic Engineering, UK (PhD 2008)


According to our database1, Qiang Liu authored at least 73 papers between 2008 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning.
ACM Trans. Reconfigurable Technol. Syst., March, 2024

Verkle-Accumulator-Based Stateless Transaction Validation (VA-STV) Scheme for the Blockchain-Based IoT Network.
IEEE Internet Things J., January, 2024

ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022).
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories.
IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization.
IEEE Trans. Computers, July, 2023

A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs.
IEEE Trans. Circuits Syst. I Regul. Pap., May, 2023

Introduction to Special Section on FPT'20.
ACM Trans. Reconfigurable Technol. Syst., March, 2023

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders.
IEEE Trans. Very Large Scale Integr. Syst., 2023

FGLQR: Factor Graph Accelerator of LQR Control for Autonomous Machines.
CoRR, 2023

An Adaptive Quantization Method for CNN Activations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

BLITZCRANK: Factor Graph Accelerator for Motion Planning.
Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022
Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs.
ACM Trans. Design Autom. Electr. Syst., 2022

RNS-Based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT.
IEEE Trans. Ind. Informatics, 2022

MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Factor Graph Accelerator for LiDAR-Inertial Odometry.
CoRR, 2022

In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU.
Proceedings of the 35th IEEE International System-on-Chip Conference, 2022

Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper).
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

LCAM: Low-Cost Approximate Multiplier Design on FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2022

DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators.
Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022

2021
Adversarial Hardware With Functional and Topological Camouflage.
IEEE Trans. Circuits Syst. II Express Briefs, 2021

Experimental Verification of EMPA Fault Mechanism.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Archytas: A Framework for Synthesizing and Dynamically Optimizing Accelerators for Robotic Localization.
Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

A Digital and Lightweight Delay-Based Detector against Fault Injection Attacks.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on FPGA.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines Industry Track Paper.
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021

An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
$\pi$π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations.
IEEE Trans. Computers, 2020

Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines.
CoRR, 2020

Peak Detection Based on FPGA Using Quasi-Newton Optimization Method for Femtosecond Laser Ranging.
IEEE Access, 2020

2019
PI-BA Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization.
CoRR, 2019

Heterogeneous Acceleration of Hybrid PSO-QN Algorithm for Neural Network Training.
IEEE Access, 2019

A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits.
IEEE Access, 2019

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks.
IEEE Access, 2019

π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019

2018
Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method.
IEEE Trans. Very Large Scale Integr. Syst., 2018

A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits.
IET Comput. Digit. Tech., 2018

2017
Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL.
Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

F-C3D: FPGA-based 3-dimensional convolutional neural network.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2016

IP Protection of Mesh NoCs Using Square Spiral Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development.
IEEE Trans. Very Large Scale Integr. Syst., 2016

A survey of hardware Trojan threat and defense.
Integr., 2016

IC security evaluation against fault injection attack based on FPGA emulation.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

Cost Effective Partial Scan for Hardware Emulation.
Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

2015
Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2015

Automating Elimination of Idle Functions by Runtime Reconfiguration.
ACM Trans. Reconfigurable Technol. Syst., 2015

Pipelined NoC router architecture design with buffer configuration exploration on FPGA.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

A Survey of Hardware Trojan Detection, Diagnosis and Prevention.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014
Comments on "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms".
IEEE Trans. Computers, 2014

Hardware Trojan detection acceleration based on word-level statistical properties management.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

2013
Automating resource optimisation in reconfigurable design (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Automating Elimination of Idle Functions by Run-Time Reconfiguration.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

2012
Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.
J. Signal Process. Syst., 2012

Optimizing Hardware Design by Composing Utility-Directed Transformations.
IEEE Trans. Computers, 2012

Neural network based pre-placement wirelength estimation.
Proceedings of the 2012 International Conference on Field-Programmable Technology, 2012

Exploiting run-time reconfiguration in stencil computation.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

Heterogeneous Systems for Energy Efficient Scientific Computing.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011
Power adaptive computing system design in energy harvesting environment.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Objective-driven workload allocation in heterogeneous computing systems.
Proceedings of the 2011 International Conference on Field-Programmable Technology, 2011

2010
Convex models for accelerating applications on FPGA-based clusters.
Proceedings of the International Conference on Field-Programmable Technology, 2010

A Scripting Engine for Combining Design Transformations.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Customizable Composition and Parameterization of Hardware Design Transformations.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

Combining optimizations in automated low power design.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A high-level compilation toolchain for heterogeneous systems.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Optimising designs by combining model-based and pattern-based transformations.
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

2008
Data Reuse and Parallelism in Hardware Compilation.
PhD thesis, 2008


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