Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm. - Konstantinos Masselos; George A. Constantinides; Qiang Liu 011 (FPL, 2006)

Automatic On-chip Memory Minimization for Data Reuse. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (FCCM, 2007)

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (BCS Int. Acad. Conf., 2008)

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (FPL, 2008)

Data Reuse and Parallelism in Hardware Compilation. - Qiang Liu 011 (2008)

Optimising designs by combining model-based and pattern-based transformations. - Qiang Liu 011; Tim Todman; José Gabriel de Figueiredo Coutinho; Wayne Luk; George A. Constantinides (FPL, 2009)

A high-level compilation toolchain for heterogeneous systems. - Wayne Luk; José Gabriel de Figueiredo Coutinho; Timothy John Todman; Yuet Ming Lam; William George Osborne; Kong Woei Susanto; Qiang Liu 011; W. S. Wong (SoCC, 2009)

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (IET Comput. Digit. Tech., 2009)

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Combining optimizations in automated low power design. - Qiang Liu 011; Tim Todman; Wayne Luk (DATE, 2010)

Customizable Composition and Parameterization of Hardware Design Transformations. - Tim Todman; Qiang Liu 011; Wayne Luk; George A. Constantinides (DSD, 2010)

A Scripting Engine for Combining Design Transformations. - Tim Todman; Qiang Liu 011; Wayne Luk; George A. Constantinides (FCCM, 2010)

Convex models for accelerating applications on FPGA-based clusters. - Qiang Liu 011; Tim Todman; Kuen Hung Tsoi; Wayne Luk (FPT, 2010)

Objective-driven workload allocation in heterogeneous computing systems. - Qiang Liu 011; Wayne Luk (FPT, 2011)

Power adaptive computing system design in energy harvesting environment. - Qiang Liu 011; Terrence S. T. Mak; Junwen Luo; Wayne Luk; Alexandre Yakovlev (ICSAMOS, 2011)

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization. - Qiang Liu 011; George A. Constantinides; Konstantinos Masselos; Peter Y. K. Cheung (Comput. J., 2011)

Heterogeneous Systems for Energy Efficient Scientific Computing. - Qiang Liu 011; Wayne Luk (ARC, 2012)

Exploiting run-time reconfiguration in stencil computation. - Xinyu Niu; Qiwei Jin; Wayne Luk; Qiang Liu 011; Oliver Pell (FPL, 2012)

Neural network based pre-placement wirelength estimation. - Qiang Liu 011; Jianguo Ma; Qijun Zhang (FPT, 2012)

Optimizing Hardware Design by Composing Utility-Directed Transformations. - Qiang Liu 011; Tim Todman; Wayne Luk; George A. Constantinides (IEEE Trans. Computers, 2012)

Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms. - Qiang Liu 011; Tim Todman; Wayne Luk; George A. Constantinides (J. Signal Process. Syst., 2012)

Automating Elimination of Idle Functions by Run-Time Reconfiguration. - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011 (FCCM, 2013)

Automating resource optimisation in reconfigurable design (abstract only). - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011 (FPGA, 2013)

Hardware Trojan detection acceleration based on word-level statistical properties management. - He Li 008; Qiang Liu 011 (FPT, 2014)

Comments on "Algorithmic Aspects of Hardware/Software Partitioning: 1D Search Algorithms". - Hao-Jun Quan; Tao Zhang 025; Qiang Liu 011; Jichang Guo; Xiaochen Wang 001; Ruimin Hu (IEEE Trans. Computers, 2014)

A Survey of Hardware Trojan Detection, Diagnosis and Prevention. - He Li 008; Qiang Liu 011; Jiliang Zhang 002; Yongqiang Lyu 001 (CAD/Graphics, 2015)

Pipelined NoC router architecture design with buffer configuration exploration on FPGA. - Qi Chen; Qiang Liu 011 (FPL, 2015)

Automating Elimination of Idle Functions by Runtime Reconfiguration. - Xinyu Niu; Thomas C. P. Chau; Qiwei Jin; Wayne Luk; Qiang Liu 011; Oliver Pell (ACM Trans. Reconfigurable Technol. Syst., 2015)

Power-Adaptive Computing System Design for Solar-Energy-Powered Embedded Systems. - Qiang Liu 011; Terrence S. T. Mak; Tao Zhang 025; Xinyu Niu; Wayne Luk; Alex Yakovlev (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Cost Effective Partial Scan for Hardware Emulation. - Tao Li; Qiang Liu 011 (FCCM, 2016)

IC security evaluation against fault injection attack based on FPGA emulation. - Song Xu; Qiang Liu 011; Tao Li; Hongxiang Fan (FPT, 2016)

A survey of hardware Trojan threat and defense. - He Li 008; Qiang Liu 011; Jiliang Zhang 002 (Integr., 2016)

Knowledge-Based Neural Network Model for FPGA Logical Architecture Development. - Qiang Liu 011; Ming Gao; Qijun Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

IP Protection of Mesh NoCs Using Square Spiral Routing. - Qiang Liu 011; Wenqing Ji; Qi Chen; Terrence S. T. Mak (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems. - Qiang Liu 011; Qijun Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Optimizing CNN-Based Object Detection Algorithms on Embedded FPGA Platforms. - Ruizhe Zhao; Xinyu Niu; Yajie Wu; Wayne Luk; Qiang Liu 011 (ARC, 2017)

F-C3D: FPGA-based 3-dimensional convolutional neural network. - Hongxiang Fan; Xinyu Niu; Qiang Liu 011; Wayne Luk (FPL, 2017)

Neural Network Training Acceleration with PSO Algorithm on a GPU Using OpenCL. - Jiajun Li; Qiang Liu 011 (HEART, 2017)

Signal word-level statistical properties-based activation approach for hardware Trojan detection in DSP circuits. - He Li 008; Qiang Liu 011; Fuqiang Chen (IET Comput. Digit. Tech., 2018)

A Low Cost Partial Scan Approach Based on Balanced Sequential Graph Transformation. - Tao Li; Qiang Liu 011 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Fast Neural Network Training on FPGA Using Quasi-Newton Optimization Method. - Qiang Liu 011; Jia Liu; Ruoyu Sang; Jiajun Li; Tao Zhang 025; Qijun Zhang (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Density-based Clustering Method for Hardware Trojan Detection Based on Gate-level Structural Features. - Pengyong Zhao; Qiang Liu 011 (AsianHOST, 2019)

π-BA: Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization. - Shuzhen Qin; Qiang Liu 011; Bo Yu 014; Shaoshan Liu (FCCM, 2019)

Information Theory-Based Quantitative Evaluation Method for Countermeasures Against Fault Injection Attacks. - Qiang Liu 011; Bo Ning 006; Pengjie Deng (IEEE Access, 2019)

A Hardware Trojan Detection Method Based on Structural Features of Trojan and Host Circuits. - Qiang Liu 011; Pengyong Zhao; Fuqiang Chen (IEEE Access, 2019)

Heterogeneous Acceleration of Hybrid PSO-QN Algorithm for Neural Network Training. - Shun Yan; Qiang Liu 011; Jiajun Li; Liang Han (IEEE Access, 2019)

PI-BA Bundle Adjustment Acceleration on Embedded FPGAs with Co-observation Optimization. - Shuzhen Qin; Qiang Liu 011; Bo Yu 014; Shaoshan Liu (CoRR, 2019)

Peak Detection Based on FPGA Using Quasi-Newton Optimization Method for Femtosecond Laser Ranging. - Yu Jiang; Qiang Liu 011; Hui Cao; Youjian Song (IEEE Access, 2020)

Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines. - Yiming Gan; Yu Bo; Boyuan Tian; Leimeng Xu; Wei Hu; Shaoshan Liu; Qiang Liu 011; Yanjun Zhang; Jie Tang 003; Yuhao Zhu 001 (CoRR, 2020)

$ pi$π-BA: Bundle Adjustment Hardware Accelerator Based on Distribution of 3D-Point Observations. - Qiang Liu 011; Shuzhen Qin; Bo Yu 014; Jie Tang 003; Shaoshan Liu (IEEE Trans. Computers, 2020)

An FPGA-based MobileNet Accelerator Considering Network Structure Characteristics. - Shun Yan; Zhengyan Liu; Yun Wang; Chenglong Zeng; Qiang Liu 011; Bowen Cheng; Ray C. C. Cheung (FPL, 2021)

Eudoxus: Characterizing and Accelerating Localization in Autonomous Machines Industry Track Paper. - Yiming Gan; Bo Yu 014; Boyuan Tian; Leimeng Xu; Wei Hu; Shaoshan Liu; Qiang Liu 011; Yanjun Zhang; Jie Tang 003; Yuhao Zhu 001 (HPCA, 2021)

Lightweight and Configurable Synchronizer and Demodulator Design for PDSCH on FPGA. - Chongguang Yao; Qiang Liu 011; Linan Wang; Qingye Zhang; Honghui Tang; Maoshen Zhang (ISCAS, 2021)

A Digital and Lightweight Delay-Based Detector against Fault Injection Attacks. - Maoshen Zhang; Qiang Liu 011 (ISCAS, 2021)

Archytas: A Framework for Synthesizing and Dynamically Optimizing Accelerators for Robotic Localization. - Weizhuang Liu; Bo Yu 014; Yiming Gan; Qiang Liu 011; Jie Tang 003; Shaoshan Liu; Yuhao Zhu 001 (MICRO, 2021)

Experimental Verification of EMPA Fault Mechanism. - Maoshen Zhang; Qiang Liu 011 (NANOARCH, 2021)

Adversarial Hardware With Functional and Topological Camouflage. - He Li 008; Ameer Abdelhadi; Runbin Shi; Jiliang Zhang 002; Qiang Liu 011 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

FPGA-Accelerated Tersoff Multi-body Potential for Molecular Dynamics Simulations. - Ming Yuan; Qiang Liu 011; Quan Deng; Shengye Xiang; Lin Gan; Jinzhe Yang; Xiaohui Duan; Haohuan Fu; Guangwen Yang (ARC, 2022)

An Energy-Efficient and Runtime-Reconfigurable FPGA-Based Accelerator for Robotic Localization Systems. - Qiang Liu 011; Zishen Wan; Bo Yu 014; Weizhuang Liu; Shaoshan Liu; Arijit Raychowdhury (CICC, 2022)

DQI: A Dynamic Quantization Method for Efficient Convolutional Neural Network Inference Accelerators. - Yun Wang; Qiang Liu 011; Shun Yan (FCCM, 2022)

LCAM: Low-Cost Approximate Multiplier Design on FPGA. - Mingyu Shu; Qiang Liu 011 (FPT, 2022)

Factor Graph Accelerator for LiDAR-Inertial Odometry (Invited Paper). - Yuhui Hao; Bo Yu 014; Qiang Liu 011; Shaoshan Liu; Yuhao Zhu 001 (ICCAD, 2022)

In-depth Analysis of the Effects of Electromagnetic Fault Injection Attack on a 32-bit MCU. - Jinteng Jiao; He Li 008; Yanzhao Feng; Chengdong Qian; Qiang Liu 011 (SOCC, 2022)

Factor Graph Accelerator for LiDAR-Inertial Odometry. - Yuhui Hao; Bo Yu 014; Qiang Liu 011; Shaoshan Liu; Yuhao Zhu 001 (CoRR, 2022)

MPFA: An Efficient Multiple Faults-Based Persistent Fault Analysis Method for Low-Cost FIA. - Honghui Tang; Qiang Liu 011 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

RNS-Based Adaptive Compression Scheme for the Block Data in the Blockchain for IIoT. - Zhaohui Guo; Zhen Gao 005; Qiang Liu 011; Chinmay Chakraborty; Qiaozhi Hua; Keping Yu; Shaohua Wan 001 (IEEE Trans. Ind. Informatics, 2022)

Fault Injection Attack Emulation Framework for Early Evaluation of IC Designs. - Qiang Liu 011; Honghui Tang; Peiran Zhang (ACM Trans. Design Autom. Electr. Syst., 2022)

BLITZCRANK: Factor Graph Accelerator for Motion Planning. - Yuhui Hao; Yiming Gan; Bo Yu 014; Qiang Liu 011; Shaoshan Liu; Yuhao Zhu 001 (DAC, 2023)

Fault Model Analysis of DRAM under Electromagnetic Fault Injection Attack. - Qiang Liu 011; Longtao Guo; Honghui Tang (DATE, 2023)

A Portable DSP Coprocessor Design Using RISC-V Packed-SIMD Instructions. - Kai Li; Wei Yin; Qiang Liu 011 (ISCAS, 2023)

An Adaptive Quantization Method for CNN Activations. - Yun Wang; Qiang Liu 011 (ISCAS, 2023)

FGLQR: Factor Graph Accelerator of LQR Control for Autonomous Machines. - Yuhui Hao; Bo Yu 014; Qiang Liu 011; Shaoshan Liu (CoRR, 2023)

Reliability Evaluation and Fault Tolerance Design for FPGA Implemented Reed Solomon (RS) Erasure Decoders. - Zhen Gao 005; Jinchang Shi; Qiang Liu 011; Anees Ullah; Pedro Reviriego (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Introduction to Special Section on FPT'20. - Oliver Sinnen; Qiang Liu 011; Azadeh Davoodi (ACM Trans. Reconfigurable Technol. Syst., 2023)

A Methodology for the Design of Fault Tolerant Parallel Digital Channelizers on SRAM-FPGAs. - Zhen Gao 005; Jiajun Xiao; Qiang Liu 011; Anees Ullah; Pedro Reviriego (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

An Energy Efficient and Runtime Reconfigurable Accelerator for Robotic Localization. - Qiang Liu 011; Yuhui Hao; Weizhuang Liu; Bo Yu 014; Yiming Gan; Jie Tang 003; Shaoshan Liu; Yuhao Zhu 001 (IEEE Trans. Computers, 2023)

Efficient Protection of FPGA Implemented LDPC Decoders Against Single Event Upsets (SEUs) on Configuration Memories. - Zhen Gao 005; Yinghao Cheng; Qiang Liu 011; Anees Ullah; Pedro Reviriego (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Guest Editorial Special Issue on the Asian Hardware Oriented Security and Trust Symposium (AsianHOST 2022). - Chip-Hong Chang; Pingqiang Zhou; Yuan Cao 003; Qiang Liu 011 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

MSCA: A Multi-Grained Sparse Convolution Accelerator for DNN Training. - Yingchang Mao; Qiang Liu 011; Ray C. C. Cheung (ASAP, 2024)

ORIANNA: An Accelerator Generation Framework for Optimization-based Robotic Applications. - Yuhui Hao; Yiming Gan; Bo Yu 014; Qiang Liu 011; Yinhe Han 001; Zishen Wan; Shaoshan Liu (ASPLOS (2), 2024)

A Data-Distribution Aware Approximate Multiplier Design Based on FPGA. - Mingyu Shu; Yingchang Mao; Qiang Liu 011 (ISCAS, 2024)

A DRAM Chip Protection Method Against EMFI Based on PHOTON Hash. - Longtao Guo; Qiang Liu 011 (ITC-Asia, 2024)

Corki: Enabling Real-time Embodied AI Robots via Algorithm-Architecture Co-Design. - Yiyang Huang; Yuhui Hao; Bo Yu 014; Feng Yan; Yuxin Yang 002; Feng Min; Yinhe Han 001; Lin Ma 002; Shaoshan Liu; Qiang Liu 011; Yiming Gan (CoRR, 2024)

Verkle-Accumulator-Based Stateless Transaction Validation (VA-STV) Scheme for the Blockchain-Based IoT Network. - Zhaohui Guo; Zhen Gao 005; Qiang Liu 011; Lei Liu 031; Mianxiong Dong; Ning Zhang 007; Mohammed Atiquzzaman (IEEE Internet Things J., 2024)

An Efficient FPGA-based Depthwise Separable Convolutional Neural Network Accelerator with Hardware Pruning. - Zhengyan Liu; Qiang Liu 011; Shun Yan; Ray C. C. Cheung (ACM Trans. Reconfigurable Technol. Syst., 2024)

AQA: An Adaptive Post-Training Quantization Method for Activations of CNNs. - Yun Wang; Qiang Liu 011 (IEEE Trans. Computers, 2024)

Modular-Based Compression Scheme for Address Data in the Blockchain System for IoV Applications. - Zhaohui Guo; Qiang Liu 011; Zhen Gao 005; Lei Liu 031; Yi Gong 002; Ximeng Liu; Neeraj Kumar 001; Mohsen Guizani (IEEE Trans. Veh. Technol., 2024)

HNMC: Hybrid Near-Memory Computing Circuit for Neural Network Acceleration. - Xiyan Liu; Qiang Liu 011 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Modeling the Effect of SEUs on the Configuration Memory of SRAM-FPGA-Based CNN Accelerators. - Zhen Gao 005; Jiaqi Feng; Shihui Gao; Qiang Liu 011; Guangjun Ge; Yu Wang 002; Pedro Reviriego (IEEE J. Emerg. Sel. Topics Circuits Syst., 2024)

Acceleration of Multi-Body Molecular Dynamics With Customized Parallel Dataflow. - Quan Deng; Qiang Liu 011; Ming Yuan; Xiaohui Duan; Lin Gan; Jinzhe Yang; Wenlai Zhao; Zhenxiang Zhang; Guiming Wu; Wayne Luk; Haohuan Fu; Guangwen Yang (IEEE Trans. Parallel Distributed Syst., 2024)

ACLAM: Accuracy-Configurable Logarithmic Approximate Floating-point Multiplier. - Zhongyu Guan; Qiang Liu 011; Guangdong Lin (ASP-DAC, 2025)

Dadu-Corki: Algorithm-Architecture Co-Design for Embodied AI-powered Robotic Manipulation. - Yiyang Huang; Yuhui Hao; Bo Yu 014; Feng Yan; Yuxin Yang 002; Feng Min; Yinhe Han 001; Lin Ma 002; Shaoshan Liu; Qiang Liu 011; Yiming Gan (ISCA, 2025)

Detect and Replace: Efficient Soft Error Protection of FPGA-Based CNN Accelerators. - Zhen Gao 005; Yanmao Qi; Jinchang Shi; Qiang Liu 011; Guangjun Ge; Yu Wang 002; Pedro Reviriego (IEEE Trans. Very Large Scale Integr. Syst., 2025)