A Micro Threading Based Concurrency Model for Parallel Computing. - Qiang Yang 006; Chris R. Jesshope; Jian Fu (IPDPS Workshops, 2011)

Apple-CORE: Microgrids of SVP Cores - Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Chris R. Jesshope (DSD, 2012)

On-demand thread-level fault detection in a concurrent programming environment. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ICSAMOS, 2013)

MGSim - A simulation environment for multi-core research and education. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (ICSAMOS, 2013)

MGSim - Simulation tools for multi-core processor architectures - Mike Lankamp; Raphael 'kena' Poss; Qiang Yang 006; Jian Fu; Muhammad Irfan Uddin; Chris R. Jesshope (CoRR, 2013)

Apple-CORE: Harnessing general-purpose many-cores with hardware concurrency management. - Raphael Poss; Mike Lankamp; Qiang Yang 006; Jian Fu; Michiel W. van Tol; Muhammad Irfan Uddin; Chris R. Jesshope (Microprocess. Microsystems, 2013)

Rethread: A Low-Cost Transient Fault Recovery Scheme for Multithreaded Processors. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (ARES, 2014)

A fault detection mechanism in a Data-flow scheduled Multithreaded processor. - Jian Fu; Qiang Yang 006; Raphael Poss; Chris R. Jesshope; Chunyuan Zhang (DATE, 2014)

On-chip traffic regulation to reduce coherence protocol cost on a microthreaded many-core architecture with distributed caches. - Qiang Yang 006; Jian Fu; Raphael Poss; Chris R. Jesshope (ACM Trans. Embed. Comput. Syst., 2014)