Qiang Zhou

According to our database1, Qiang Zhou authored at least 139 papers between 2004 and 2018.

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Bibliography

2018
A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

Spear and Shield: Evolution of Integrated Circuit Camouflaging.
J. Comput. Sci. Technol., 2018

Look at Boundary: A Boundary-Aware Face Alignment Algorithm.
CoRR, 2018

Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks.
Proceedings of the 2018 International Conference on Computing, 2018

Electromagnetic equalizer: an active countermeasure against EM side-channel attack.
Proceedings of the International Conference on Computer-Aided Design, 2018

Electromigration Design Rule aware Global and Detailed Routing Algorithm.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Look at Boundary: A Boundary-Aware Face Alignment Algorithm.
Proceedings of the 2018 IEEE Conference on Computer Vision and Pattern Recognition, 2018

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

ASAX: Automatic security assertion extraction for detecting Hardware Trojans.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

HLIFT: A high-level information flow tracking method for detecting hardware Trojans.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
An Effective Power Grid Optimization Approach for the Electromigration Reliability.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Crossover Ring Oscillator PUF.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Cell spreading optimization for force-directed global placers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

2016
Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function.
J. Comput. Sci. Technol., 2016

Is the Secure IC camouflaging really secure?
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An efficient framework for configurable RO PUF.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015
A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification.
IEEE Trans. VLSI Syst., 2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.
IEEE Trans. VLSI Syst., 2015

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths.
J. Comput. Sci. Technol., 2015

Register Clustering Methodology for Low Power Clock Tree Synthesis.
J. Comput. Sci. Technol., 2015

SIAR: Customized real-time interactive router for analog circuits.
Integration, 2015

Fast synthesis of low power clock trees based on register clustering.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators.
Proceedings of the 14th International Conference on Computer-Aided Design and Computer Graphics, 2015

2014
PowerRush: An Efficient Simulator for Static Power Grid Analysis.
IEEE Trans. VLSI Syst., 2014

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis.
IEEE Trans. VLSI Syst., 2014

Length matching in detailed routing for analog and mixed signal circuits.
Microelectronics Journal, 2014

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs.
J. Comput. Sci. Technol., 2014

Trusted Integrated Circuits: The Problem and Challenges.
J. Comput. Sci. Technol., 2014

RSMT construction algorithm based on Congestion-Oriented Flexibility.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

A register clustering algorithm for low power clock tree synthesis.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Accurate prediction of detailed routing congestion using supervised data learning.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

MCFRoute: a detailed router based on multi-commodity flow method.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Power supply noise aware evaluation framework for side channel attacks and countermeasures.
Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

VFGR: A very fast parallel global router with accurate congestion modeling.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs.
Integration, 2013

Selected inversion for vectorless power grid verification by exploiting locality.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Design and implementation of a group-based RO PUF.
Proceedings of the Design, Automation and Test in Europe, 2013

Design and Implementation of a Delay-Based PUF for FPGA IP Protection.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model.
Proceedings of the 2013 International Conference on Computer-Aided Design and Computer Graphics, 2013

A new splitting graph construction algorithm for SIAR router.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

Analog routing considering min-area constraint.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
TimFastPlace: Critical-path based timing driven FastPlace.
IEICE Electronic Express, 2012

A DyadicCluster method used for nonlinear placement.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

PowerRush : Efficient transient simulation for power grid analysis.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

Thermal-aware power network design for IR drop reduction in 3D ICs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs.
IEEE Trans. VLSI Syst., 2011

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A novel fine-grain track routing approach for routability and crosstalk optimization.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

PowerRush: A linear simulator for power grid.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Fast poisson solver preconditioned method for robust power grid analysis.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

SIAR: splitting-graph-based interactive analog router.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

A fast recursive detailed routing algorithm for hierarchical FPGAs.
Proceedings of the 2011 15th International Conference on Computer Supported Cooperative Work in Design, 2011

A timing-perspective study on the wire model in placement.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
ECP- and CMP-Aware Detailed Routing Algorithm for DFM.
IEEE Trans. VLSI Syst., 2010

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement.
J. Comput. Sci. Technol., 2010

Thermal Impacts of Leakage Power in 2D/3D floorplanning.
Journal of Circuits, Systems, and Computers, 2010

Useful clock skew optimization under a multi-corner multi-mode design framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

A low power clock network placement framework.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Peak current reduction by simultaneous state replication and re-encoding.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Behavioral level dual-vth design for reduced leakage power with thermal awareness.
Proceedings of the Design, Automation and Test in Europe, 2010

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal.
Proceedings of the Design, Automation and Test in Europe, 2010

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA.
Proceedings of the 2010 14th International Conference on Computer Supported Cooperative Work in Design, 2010

2009
An MTCMOS technology for low-power physical design.
Integration, 2009

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach.
Integration, 2009

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation.
IEICE Transactions, 2009

Cell shifting aware of wirelength and overlap.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Decoupling capacitance efficient placement for reducing transient power supply noise.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Fast congestion-aware timing-driven placement for island FPGA.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Improve clock gating through power-optimal enable function selection.
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009

Information hiding for trusted system design.
Proceedings of the 46th Design Automation Conference, 2009

Global density smoothing technique for analytical placement algorithm.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

A thermal-driven force-directed floorplanning algorithm for 3D ICs.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Fast placement for large-scale hierarchical FPGAs.
Proceedings of the 11th International Conference on Computer-Aided Design and Computer Graphics, 2009

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage.
IEICE Transactions, 2008

Application of optical proximity correction technology.
Science in China Series F: Information Sciences, 2008

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

DFM Based Detailed Routing Algorithm for ECP and CMP.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A novel performance driven power gating based on distributed sleep transistor network.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation.
Proceedings of the FPL 2008, 2008

Low power clock buffer planning methodology in F-D placement for large scale circuit design.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Wire density driven top-down global placement for CMP variation control.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

A Yield-Driven Gridless Router.
J. Comput. Sci. Technol., 2007

An efficient quadratic placement based on search space traversing technology.
Integration, 2007

Voltage Island Generation in Cell Based Dual-Vdd Design.
IEICE Transactions, 2007

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Power Delivery Aware Floorplanning for Voltage Island Designs.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

New timing and routability driven placement algorithms for FPGA synthesis.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR.
Proceedings of the 10th International Conference on Computer-Aided Design and Computer Graphics, 2007

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

Logic and Layout Aware Voltage Island Generation for Low Power Design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration.
ACM Trans. Design Autom. Electr. Syst., 2006

Multilevel Routing With Redundant Via Insertion.
IEEE Trans. on Circuits and Systems, 2006

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization.
IEEE Trans. on Circuits and Systems, 2006

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment.
IEEE Trans. on Circuits and Systems, 2006

Priority-Based Routing Resource Assignment Considering Crosstalk.
J. Comput. Sci. Technol., 2006

Integrating dynamic thermal via planning with 3D floorplanning algorithm.
Proceedings of the 2006 International Symposium on Physical Design, 2006

A novel low-power physical design methodology for MTCMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A novel technique integrating buffer insertion into timing driven placement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Crosstalk-Aware Routing Resource Assignment.
J. Comput. Sci. Technol., 2005

Shielding Area Optimization Under the Solution of Interconnect Crosstalk.
J. Comput. Sci. Technol., 2005

A Fast Delay Computation for the Hybrid Structured Clock Network.
IEICE Transactions, 2005

Navigating Register Placement for Low Power Clock Network Design.
IEICE Transactions, 2005

Crosstalk and Congestion Driven Layer Assignment Algorithm.
IEICE Transactions, 2005

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design.
Proceedings of the Integrated Circuit and System Design, 2005

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Integrated routing resource assignment for RLC crosstalk minimization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design.
Proceedings of the Embedded Software and Systems, Second International Conference, 2005

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design.
Proceedings of the Computational Science and Its Applications, 2005

Improved multilevel routing with redundant via placement for yield and reliability.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

A new algorithm for layout of dark field alternating phase shifting masks.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Navigating registers in placement for clock network minimization.
Proceedings of the 42nd Design Automation Conference, 2005

Analysis of buffered hybrid structured clock networks.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Register placement for low power clock network.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Clock network minimization methodology based on incremental placement.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Shielding area optimization under the solution of interconnect crosstalk.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Crosstalk driven routing resource assignment.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Algorithm for yield driven correction of layout.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Layer assignment algorithm for RLC crosstalk minimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004


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