A Fast Delay Analysis Algorithm for The Hybrid Structured Clock Network. - Yi Zou; Yici Cai; Qiang Zhou 001; Xianlong Hong; Sheldon X.-D. Tan (ICCD, 2004)

Layer assignment algorithm for RLC crosstalk minimization. - Bin Liu 007; Yici Cai; Qiang Zhou 001; Xianlong Hong (ISCAS (5), 2004)

Algorithm for yield driven correction of layout. - Yang Wang; Yici Cai; Xianlong Hong; Qiang Zhou 001 (ISCAS (5), 2004)

Recursively combine floorplan and Q-place in mixed mode placement based on circuit's variety of block configuration. - Changqi Yang; Xianlong Hong; Hannah Honghua Yang; Qiang Zhou 001; Yici Cai; Yongqiang Lu 001 (ISCAS (5), 2004)

Crosstalk driven routing resource assignment. - Hailong Yao; Qiang Zhou 001; Xianlong Hong; Yici Cai (ISCAS (5), 2004)

Shielding area optimization under the solution of interconnect crosstalk. - Xin Zhao; Yici Cai; Qiang Zhou 001; Xianlong Hong; Lei He 001; Jinjun Xiong (ISCAS (5), 2004)

Clock network minimization methodology based on incremental placement. - Liang Huang; Yici Cai; Qiang Zhou 001; Xianlong Hong; Jiang Hu; Yongqiang Lu 001 (ASP-DAC, 2005)

Register placement for low power clock network. - Yongqiang Lu 001; Cliff C. N. Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (ASP-DAC, 2005)

Analysis of buffered hybrid structured clock networks. - Yi Zou; Qiang Zhou 001; Yici Cai; Xianlong Hong; Sheldon X.-D. Tan (ASP-DAC, 2005)

Navigating registers in placement for clock network minimization. - Yongqiang Lu 001; Cliff C. N. Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (DAC, 2005)

A new algorithm for layout of dark field alternating phase shifting masks. - Qinglang Luo; Xianlong Hong; Qiang Zhou 001; Yici Cai (ACM Great Lakes Symposium on VLSI, 2005)

Improved multilevel routing with redundant via placement for yield and reliability. - Hailong Yao; Yici Cai; Xianlong Hong; Qiang Zhou 001 (ACM Great Lakes Symposium on VLSI, 2005)

Multi-stage Detailed Placement Algorithm for Large-Scale Mixed-Mode Layout Design. - Lijuan Luo; Qiang Zhou 001; Xianlong Hong; Hanbin Zhou (ICCSA (4), 2005)

A New Methodology of Integrating High Level Synthesis and Floorplan for SoC Design. - Yunfeng Wang; Jinian Bian; Xianlong Hong; Liu Yang; Qiang Zhou 001; Qiang Wu (ICESS, 2005)

A Hybrid Genetic Algorithm and Application to the Crosstalk Aware Track Assignment Problem. - Yici Cai; Bin Liu 007; Xiong Yan; Qiang Zhou 001; Xianlong Hong (ICNC (3), 2005)

Integrated routing resource assignment for RLC crosstalk minimization. - Yici Cai; Bin Liu 007; Qiang Zhou 001; Xianlong Hong (ISCAS (2), 2005)

A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannal Yang; Prashant Saxena; Vijay Pitchumani (ISCAS (6), 2005)

A Thermal Aware Floorplanning Algorithm Supporting Voltage Islands for Low Power SOC Design. - Yici Cai; Bin Liu 007; Qiang Zhou 001; Xianlong Hong (PATMOS, 2005)

Crosstalk and Congestion Driven Layer Assignment Algorithm. - Bin Liu 007; Yici Cai; Qiang Zhou 001; Xianlong Hong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Navigating Register Placement for Low Power Clock Network Design. - Yongqiang Lu 001; Chin Ngai Sze; Xianlong Hong; Qiang Zhou 001; Yici Cai; Liang Huang; Jiang Hu (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A Fast Delay Computation for the Hybrid Structured Clock Network. - Yi Zou; Yici Cai; Qiang Zhou 001; Xianlong Hong; Sheldon X.-D. Tan (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

Shielding Area Optimization Under the Solution of Interconnect Crosstalk. - Yici Cai; Xin Zhao; Qiang Zhou 001; Xianlong Hong (J. Comput. Sci. Technol., 2005)

Crosstalk-Aware Routing Resource Assignment. - Hailong Yao; Yici Cai; Qiang Zhou 001; Xianlong Hong (J. Comput. Sci. Technol., 2005)

Variational Circuit Simulator based on a Unified Methodology using Arithmetic over Taylor Polynomials. - Qiang Zhou 001; Yi Zou; Yici Cai; Xianlong Hong (APCCAS, 2006)

Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. - Bin Liu 007; Yici Cai; Qiang Zhou 001; Xianlong Hong (ASP-DAC, 2006)

A novel technique integrating buffer insertion into timing driven placement. - Lijuan Luo; Qiang Zhou 001; Yici Cai; Xianlong Hong; Yibo Wang 009 (ISCAS, 2006)

A novel low-power physical design methodology for MTCMOS. - Xin Zhao; Yici Cai; Qiang Zhou 001; Xianlong Hong (ISCAS, 2006)

Integrating dynamic thermal via planning with 3D floorplanning algorithm. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (ISPD, 2006)

Priority-Based Routing Resource Assignment Considering Crosstalk. - Yici Cai; Bin Liu 007; Yan Xiong 001; Qiang Zhou 001; Xianlong Hong (J. Comput. Sci. Technol., 2006)

A Two-Step Heuristic Algorithm for Minimum-Crosstalk Routing Resource Assignment. - Yici Cai; Bin Liu 007; Qiang Zhou 001; Xianlong Hong (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Hierarchical 3-D Floorplanning Algorithm for Wirelength Optimization. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Circuits Syst. I Regul. Pap., 2006)

Multilevel Routing With Redundant Via Insertion. - Hailong Yao; Yici Cai; Qiang Zhou 001; Xianlong Hong (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Jinian Bian; Hannah Honghua Yang; Vijay Pitchumani (ACM Trans. Design Autom. Electr. Syst., 2006)

Logic and Layout Aware Voltage Island Generation for Low Power Design. - Liangpeng Guo; Yici Cai; Qiang Zhou 001; Xianlong Hong (ASP-DAC, 2007)

Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning. - Yuchun Ma; Zhuoyuan Li 003; Jason Cong; Xianlong Hong; Glenn Reinman; Sheqin Dong; Qiang Zhou 001 (ASP-DAC, 2007)

Practical Implementation of Stochastic Parameterized Model Order Reduction via Hermite Polynomial Chaos. - Yi Zou; Yici Cai; Qiang Zhou 001; Xianlong Hong; Sheldon X.-D. Tan; Le Kang (ASP-DAC, 2007)

VPH: Versatile Routability-Driven Place Algorithm for Hierarchical FPGAs Based on VPR. - Yanhua Wang; Qiang Zhou 001; Jinian Bian; Junhua Qu (CAD/Graphics, 2007)

Thermal Effects with Leakage Power Considered in 2D/3D Floorplanning. - Pingqiang Zhou; Yuchun Ma; Qiang Zhou 001; Xianlong Hong (CAD/Graphics, 2007)

New timing and routability driven placement algorithms for FPGA synthesis. - Yue Zhuo; Hao Li 030; Qiang Zhou 001; Yici Cai; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2007)

3D-STAF: scalable temperature and leakage aware floorplanning for three-dimensional integrated circuits. - Pingqiang Zhou; Yuchun Ma; Zhuoyuan Li 003; Robert P. Dick; Li Shang; Hai Zhou 001; Xianlong Hong; Qiang Zhou 001 (ICCAD, 2007)

Clock-Tree Aware Placement Based on Dynamic Clock-Tree Building. - Yanfeng Wang; Qiang Zhou 001; Xianlong Hong; Yici Cai (ISCAS, 2007)

Unified Quadratic Programming Approach For 3-D Mixed Mode Placement. - Haixia Yan; Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001 (ISCAS, 2007)

Power Delivery Aware Floorplanning for Voltage Island Designs. - Yici Cai; Bin Liu 007; Jin Shi; Qiang Zhou 001; Xianlong Hong (ISQED, 2007)

Interconnect Delay and Power Optimization by Module Duplication for Integration of High Level Synthesis and Floorplan. - Zhipeng Liu; Jinian Bian; Qiang Zhou 001; Hui Dai (ISVLSI, 2007)

Voltage Island Generation in Cell Based Dual-Vdd Design. - Yici Cai; Bin Liu 007; Qiang Zhou 001; Xianlong Hong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007)

An efficient quadratic placement based on search space traversing technology. - Yongqiang Lu 001; Xianlong Hong; Qiang Zhou 001; Yici Cai; Jun Gu (Integr., 2007)

A Yield-Driven Gridless Router. - Qiang Zhou 001; Yici Cai; Duo Li; Xianlong Hong (J. Comput. Sci. Technol., 2007)

Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning. - Zhuoyuan Li 003; Xianlong Hong; Qiang Zhou 001; Shan Zeng; Jinian Bian; Wenjian Yu; Hannah Honghua Yang; Vijay Pitchumani; Chung-Kuan Cheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Wire density driven top-down global placement for CMP variation control. - Changdao Dong; Qiang Zhou 001; Yici Cai; Xianlong Hong (APCCAS, 2008)

Low power clock buffer planning methodology in F-D placement for large scale circuit design. - Yanfeng Wang; Qiang Zhou 001; Yici Cai; Jiang Hu; Xianlong Hong; Jinian Bian (ASP-DAC, 2008)

MacroMap: A technology mapping algorithm for heterogeneous FPGAs with effective area estimation. - Xing Wei; Juanjuan Chen; Qiang Zhou 001; Yici Cai; Jinian Bian; Xianlong Hong (FPL, 2008)

A novel performance driven power gating based on distributed sleep transistor network. - Liangpeng Guo; Yici Cai; Qiang Zhou 001; Le Kang; Xianlong Hong (ACM Great Lakes Symposium on VLSI, 2008)

DFM Based Detailed Routing Algorithm for ECP and CMP. - Yin Shen; Yici Cai; Qiang Zhou 001; Xianlong Hong (ISQED, 2008)

Efficient Thermal Aware Placement Approach Integrated with 3D DCT Placement Algorithm. - Haixia Yan; Qiang Zhou 001; Xianlong Hong (ISQED, 2008)

Application of optical proximity correction technology. - Yici Cai; Qiang Zhou 001; Xianlong Hong; Rui Shi; Yang Wang (Sci. China Ser. F Inf. Sci., 2008)

Logic and Layout Aware Level Converter Optimization for Multiple Supply Voltage. - Liangpeng Guo; Yici Cai; Qiang Zhou 001; Xianlong Hong (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

Peak temperature control in thermal-aware behavioral synthesis through allocating the number of resources. - Junbo Yu; Qiang Zhou 001; Jinian Bian (ASP-DAC, 2009)

Fast placement for large-scale hierarchical FPGAs. - Hui Dai; Qiang Zhou 001; Yici Cai; Jinian Bian; Xianlong Hong (CAD/Graphics, 2009)

A thermal-driven force-directed floorplanning algorithm for 3D ICs. - Yun Huang; Qiang Zhou 001; Yici Cai; Haixia Yan (CAD/Graphics, 2009)

Global density smoothing technique for analytical placement algorithm. - Dawei Liu; Qiang Zhou 001; Jinian Bian; Yanming Jia (CAD/Graphics, 2009)

Information hiding for trusted system design. - Junjun Gu; Gang Qu 001; Qiang Zhou 001 (DAC, 2009)

Improve clock gating through power-optimal enable function selection. - Juanjuan Chen; Xing Wei; Yunjian Jiang; Qiang Zhou 001 (DDECS, 2009)

Fast congestion-aware timing-driven placement for island FPGA. - Jinpeng Zhao; Qiang Zhou 001; Yici Cai (DDECS, 2009)

Decoupling capacitance efficient placement for reducing transient power supply noise. - Xiaoyi Wang; Yici Cai; Qiang Zhou 001; Sheldon X.-D. Tan; Thom Jefferson A. Eguia (ICCAD, 2009)

Cell shifting aware of wirelength and overlap. - Dawei Liu; Qiang Zhou 001; Jinian Bian; Yici Cai; Xianlong Hong (ISQED, 2009)

Peak Temperature Reduction by Physical Information Driven Behavioral Synthesis with Resource Usage Allocation. - Junbo Yu; Qiang Zhou 001; Gang Qu 001; Jinian Bian (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Thermal aware placement in 3D ICs using quadratic uniformity modeling approach. - Haixia Yan; Qiang Zhou 001; Xianlong Hong (Integr., 2009)

An MTCMOS technology for low-power physical design. - Qiang Zhou 001; Xin Zhao; Yici Cai; Xianlong Hong (Integr., 2009)

An architecture-aware routing optimization via satisfiabilty for hierarchical FPGA. - Limin Zhu; Qiang Zhou 001; Yici Cai; Jinian Bian (CSCWD, 2010)

SAT based multi-net rip-up-and-reroute for manufacturing hotspot removal. - Fan Yang; Yici Cai; Qiang Zhou 001; Jiang Hu (DATE, 2010)

Behavioral level dual-vth design for reduced leakage power with thermal awareness. - Junbo Yu; Qiang Zhou 001; Gang Qu 001; Jinian Bian (DATE, 2010)

Peak current reduction by simultaneous state replication and re-encoding. - Junjun Gu; Gang Qu 001; Lin Yuan; Qiang Zhou 001 (ICCAD, 2010)

A low power clock network placement framework. - Dawei Liu; Qiang Zhou 001; Yongqiang Lu 001; Jinian Bian (ISQED, 2010)

Useful clock skew optimization under a multi-corner multi-mode design framework. - Weixiang Shen; Yici Cai; Wei Chen 070; Yongqiang Lu 001; Qiang Zhou 001; Jiang Hu (ISQED, 2010)

Thermal Impacts of Leakage Power in 2D/3D floorplanning. - Yuchun Ma; Qiang Zhou 001; Pingqiang Zhou; Xianlong Hong (J. Circuits Syst. Comput., 2010)

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement. - Hui Dai; Qiang Zhou 001; Jinian Bian (J. Comput. Sci. Technol., 2010)

ECP- and CMP-Aware Detailed Routing Algorithm for DFM. - Yin Shen; Qiang Zhou 001; Yici Cai; Xianlong Hong (IEEE Trans. Very Large Scale Integr. Syst., 2010)

A timing-perspective study on the wire model in placement. - Liu Liu; Yongqiang Lu 001; Qiang Zhou 001 (ASICON, 2011)

A fast recursive detailed routing algorithm for hierarchical FPGAs. - Limin Zhu; Jinian Bian; Qiang Zhou 001; Yici Cai (CSCWD, 2011)

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. - Feifei Niu; Qiang Zhou 001; Hailong Yao; Yici Cai; Jianlei Yang 001; Chin Ngai Sze (ACM Great Lakes Symposium on VLSI, 2011)

SIAR: splitting-graph-based interactive analog router. - Fan Yang; Hailong Yao; Qiang Zhou 001; Yici Cai (ACM Great Lakes Symposium on VLSI, 2011)

Fast poisson solver preconditioned method for robust power grid analysis. - Jianlei Yang 001; Yici Cai; Qiang Zhou 001; Jin Shi (ICCAD, 2011)

PowerRush: A linear simulator for power grid. - Jianlei Yang 001; Zuowei Li; Yici Cai; Qiang Zhou 001 (ICCAD, 2011)

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. - Qiang Gao; Hailong Yao; Qiang Zhou 001; Yici Cai (ISQED, 2011)

A novel fine-grain track routing approach for routability and crosstalk optimization. - Zhongdong Qi; Qiang Zhou 001; Yanming Jia; Yici Cai; Zhuoyuan Li 003; Hailong Yao (ISQED, 2011)

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. - Shuzhe Zhou; Hailong Yao; Qiang Zhou 001; Yici Cai (ISVLSI, 2011)

Floorplanning Considering IR Drop in Multiple Supply Voltages Island Designs. - Qiang Zhou 001; Jin Shi; Bin Liu 007; Yici Cai (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Thermal-aware power network design for IR drop reduction in 3D ICs. - Zuowei Li; Yuchun Ma; Qiang Zhou 001; Yici Cai; Yu Wang 002; Tingting Huang; Yuan Xie 001 (ASP-DAC, 2012)

PowerRush : Efficient transient simulation for power grid analysis. - Jianlei Yang 001; Zuowei Li; Yici Cai; Qiang Zhou 001 (ICCAD, 2012)

A DyadicCluster method used for nonlinear placement. - Wenchao Gao; Qiang Zhou 001; Xu Qian; Yici Cai (ISQED, 2012)

TimFastPlace: Critical-path based timing driven FastPlace. - Jiliang Zhang 002; Yongqiang Lu 001; Qiang Zhou 001; Qiang Wu; Yaping Lin; Kang Zhao (IEICE Electron. Express, 2012)

Analog routing considering min-area constraint. - Weijie Chen; Hailong Yao; Yici Cai; Qiang Zhou 001 (ASICON, 2013)

A new splitting graph construction algorithm for SIAR router. - Jinming Zhao; Hailong Yao; Yici Cai; Qiang Zhou 001 (ASICON, 2013)

Bridging the Gap between Global Routing and Detailed Routing: A Practical Congestion Model. - Zhongdong Qi; Yici Cai; Qiang Zhou 001 (CAD/Graphics, 2013)

Design and Implementation of a Delay-Based PUF for FPGA IP Protection. - Jiliang Zhang 002; Qiang Wu; Yongqiang Lyu 001; Qiang Zhou 001; Yici Cai; Yaping Lin; Gang Qu 001 (CAD/Graphics, 2013)

Design and implementation of a group-based RO PUF. - Chi-En Daniel Yin; Gang Qu 001; Qiang Zhou 001 (DATE, 2013)

Binding Hardware IPs to Specific FPGA Device via Inter-twining the PUF Response with the FSM of Sequential Circuits. - Jiliang Zhang 002; Yaping Lin; Yongqiang Lu 001; Ray C. C. Cheung; Wenjie Che; Qiang Zhou 001; Jinian Bian (FCCM, 2013)

FPGA IP protection by binding Finite State Machine to Physical Unclonable Function. - Jiliang Zhang 002; Yaping Lin; Yongqiang Lyu 001; Gang Qu 001; Ray C. C. Cheung; Wenjie Che; Qiang Zhou 001; Jinian Bian (FPL, 2013)

Selected inversion for vectorless power grid verification by exploiting locality. - Jianlei Yang 001; Yici Cai; Qiang Zhou 001; Wei Zhao (ICCD, 2013)

Thermal-aware P/G TSV planning for IR drop reduction in 3D ICs. - Zuowei Li; Yuchun Ma; Qiang Zhou 001; Yici Cai; Yuan Xie 001; Tingting Huang (Integr., 2013)

VFGR: A very fast parallel global router with accurate congestion modeling. - Zhongdong Qi; Yici Cai; Qiang Zhou 001; Zhuoyuan Li 003; Mike Chen (ASP-DAC, 2014)

Power supply noise aware evaluation framework for side channel attacks and countermeasures. - Jianlei Yang 001; Chenguang Wang 003; Yici Cai; Qiang Zhou 001 (FPT, 2014)

MCFRoute: a detailed router based on multi-commodity flow method. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Gang Chen; Zhuoyuan Li 003; Zuowei Li (ICCAD, 2014)

Accurate prediction of detailed routing congestion using supervised data learning. - Zhongdong Qi; Yici Cai; Qiang Zhou 001 (ICCD, 2014)

A register clustering algorithm for low power clock tree synthesis. - Chao Deng; Yici Cai; Qiang Zhou 001 (ISCAS, 2014)

RSMT construction algorithm based on Congestion-Oriented Flexibility. - Ziyang Qi; Kun Ma; Qiang Zhou 001; Yici Cai (LASCAS, 2014)

Trusted Integrated Circuits: The Problem and Challenges. - Yong-Qiang Lv 001; Qiang Zhou 001; Yici Cai; Gang Qu 001 (J. Comput. Sci. Technol., 2014)

A Survey on Silicon PUFs and Recent Advances in Ring Oscillator PUFs. - Jiliang Zhang 002; Gang Qu 001; Yong-Qiang Lv 001; Qiang Zhou 001 (J. Comput. Sci. Technol., 2014)

Length matching in detailed routing for analog and mixed signal circuits. - Hailong Yao; Qiang Gao; Yici Cai; Qiang Zhou 001; Chiu-Wing Sham (Microelectron. J., 2014)

Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. - Jianlei Yang 001; Yici Cai; Qiang Zhou 001; Jin Shi (IEEE Trans. Very Large Scale Integr. Syst., 2014)

PowerRush: An Efficient Simulator for Static Power Grid Analysis. - Jianlei Yang 001; Zuowei Li; Yici Cai; Qiang Zhou 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators. - Mingze Gao; Khai Lai; Jiliang Zhang 002; Gang Qu 001; Aijiao Cui; Qiang Zhou 001 (CAD/Graphics, 2015)

Fast synthesis of low power clock trees based on register clustering. - Chao Deng; Yici Cai; Qiang Zhou 001 (ISQED, 2015)

SIAR: Customized real-time interactive router for analog circuits. - Hailong Yao; Fan Yang; Yici Cai; Qiang Zhou 001; Chiu-Wing Sham (Integr., 2015)

Register Clustering Methodology for Low Power Clock Tree Synthesis. - Chao Deng; Yici Cai; Qiang Zhou 001 (J. Comput. Sci. Technol., 2015)

Design-Rule-Aware Congestion Model with Explicit Modeling of Vias and Local Pin Access Paths. - Zhongdong Qi; Yici Cai; Qiang Zhou 001 (J. Comput. Sci. Technol., 2015)

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. - Yici Cai; Chao Deng; Qiang Zhou 001; Hailong Yao; Feifei Niu; Cliff N. Sze (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. - Jianlei Yang 001; Yici Cai; Qiang Zhou 001; Wei Zhao (IEEE Trans. Very Large Scale Integr. Syst., 2015)

MCFRoute 2.0: A Redundant Via Insertion Enhanced Concurrent Detailed Router. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ACM Great Lakes Symposium on VLSI, 2016)

Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. - Xueyan Wang; Xiaotao Jia; Qiang Zhou 001; Yici Cai; Jianlei Yang 001; Mingze Gao; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2016)

An efficient framework for configurable RO PUF. - Zhuwei Chen; Yici Cai; Qiang Zhou 001; Gang Qu 001 (ISCAS, 2016)

Is the Secure IC camouflaging really secure? - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (ISCAS, 2016)

Techniques for Design and Implementation of an FPGA-Specific Physical Unclonable Function. - Jiliang Zhang 002; Qiang Wu; Yipeng Ding; Yong-Qiang Lv 001; Qiang Zhou 001; Zhihua Xia; Xingming Sun; Xing-Wei Wang 001 (J. Comput. Sci. Technol., 2016)

An Empirical Study on Gate Camouflaging Methods Against Circuit Partition Attack. - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (ACM Great Lakes Symposium on VLSI, 2017)

Automatic Security Property Generation for Detecting Information-Leaking Hardware Trojans. - Chenguang Wang 003; Yici Cai; Qiang Zhou 001 (ICCD, 2017)

Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. - Chenguang Wang 003; Ming Yan; Yici Cai; Qiang Zhou 001; Jianlei Yang 001 (ICCD, 2017)

Cell spreading optimization for force-directed global placers. - Xueyan Wang; Yici Cai; Qiang Zhou 001 (ISCAS, 2017)

Crossover Ring Oscillator PUF. - Zihan Pang; Jiliang Zhang 002; Qiang Zhou 001; Shuqian Gong; Xu Qian; Bin Tang (ISQED, 2017)

An Effective Power Grid Optimization Approach for the Electromigration Reliability. - Ming Yan; Yici Cai; Chenguang Wang 003; Qiang Zhou 001 (ISVLSI, 2017)

HLIFT: A high-level information flow tracking method for detecting hardware Trojans. - Chenguang Wang 003; Yici Cai; Qiang Zhou 001 (ASP-DAC, 2018)

ASAX: Automatic security assertion extraction for detecting Hardware Trojans. - Chenguang Wang 003; Yici Cai; Qiang Zhou 001; Haoyi Wang (ASP-DAC, 2018)

A conflict-free approach for parallelizing SAT-based de-camouflaging attacks. - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (ASP-DAC, 2018)

Look at Boundary: A Boundary-Aware Face Alignment Algorithm. - Wayne Wu; Chen Qian 006; Shuo Yang 003; Quan Wang; Yici Cai; Qiang Zhou 001 (CVPR, 2018)

Electromigration Design Rule aware Global and Detailed Routing Algorithm. - Xiaotao Jia; Jing Wang 224; Yici Cai; Qiang Zhou 001 (ACM Great Lakes Symposium on VLSI, 2018)

Electromagnetic equalizer: an active countermeasure against EM side-channel attack. - Chenguang Wang 003; Yici Cai; Haoyi Wang; Qiang Zhou 001 (ICCAD, 2018)

Poet-based Poetry Generation: Controlling Personal Style with Recurrent Neural Networks. - Jia Wei; Qiang Zhou 001; Yici Cai (ICNC, 2018)

An Efficient Technique to Reverse Engineer Minterm Protection Based Camouflaged Circuit. - Shan Jiang; Ning Xu 006; Xueyan Wang; Qiang Zhou 001 (J. Comput. Sci. Technol., 2018)

Spear and Shield: Evolution of Integrated Circuit Camouflaging. - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (J. Comput. Sci. Technol., 2018)

Experimental investigation on climbing robot using rotation-flow adsorption unit. - Qiang Zhou 001; Xin Li 085 (Robotics Auton. Syst., 2018)

A Multicommodity Flow-Based Detailed Router With Efficient Acceleration Techniques. - Xiaotao Jia; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

FAB: A Robust Facial Landmark Detection Framework for Motion-Blurred Videos. - Keqiang Sun; Wayne Wu; Tinghao Liu; Shuo Yang 003; Quan Wang; Qiang Zhou 001; Zuochang Ye; Chen Qian 006 (ICCV, 2019)

Composite Optimization for Electromigration Reliability and Noise in Power Grid Networks. - Jing Wang 224; Yici Cai; Ming Yan; Qiang Zhou 001 (ISCAS, 2019)

Deep coupling neural network for robust facial landmark detection. - Wenyan Wu 005; Xingzhe Wu; Yici Cai; Qiang Zhou 001 (Comput. Graph., 2019)

A high-level information flow tracking method for detecting information leakage. - Haoyi Wang; Chenguang Wang 003; Yici Cai; Qiang Zhou 001 (Integr., 2019)

Parallelizing SAT-based de-camouflaging attacks by circuit partitioning and conflict avoiding. - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (Integr., 2019)

Toward a Formal and Quantitative Evaluation Framework for Circuit Obfuscation Methods. - Xueyan Wang; Qiang Zhou 001; Yici Cai; Gang Qu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. - Jianlei Yang 001; Xueyan Wang; Qiang Zhou 001; Zhaohao Wang; Hai Li 001; Yiran Chen 001; Weisheng Zhao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

TransMoMo: Invariance-Driven Unsupervised Video Motion Retargeting. - Zhuoqian Yang; Wentao Zhu 004; Wayne Wu; Chen Qian 006; Qiang Zhou 001; Bolei Zhou; Chen Change Loy (CVPR, 2020)

Instant-Teaching: An End-to-End Semi-Supervised Object Detection Framework. - Qiang Zhou 001; Chaohui Yu; Zhibin Wang 004; Qi Qian 001; Hao Li 030 (CVPR, 2021)

SRL: Separation-and-Recombination Learning for Video Facial Landmark Detection with Limited Data. - Wenyan Wu 005; Yici Cai; Qiang Zhou 001 (FG, 2021)

McPAT-Calib: A Microarchitecture Power Modeling Framework for Modern CPUs. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (ICCAD, 2021)

LUAI Challenge 2021 on Learning to Understand Aerial Images. - Gui-Song Xia; Jian Ding 001; Ming Qian; Nan Xue 001; Jiaming Han; Xiang Bai; Michael Ying Yang; Shengyang Li; Serge J. Belongie; Jiebo Luo 001; Mihai Datcu; Marcello Pelillo; et al. (ICCVW, 2021)

Multiple Features Driven Author Name Disambiguation. - Qiang Zhou 001; Wei Chen 070; Weiqing Wang 001; Jiajie Xu 001; Lei Zhao 001 (ICWS, 2021)

An Efficient Approach for DRC Hotspot Prediction with Convolutional Neural Network. - Lin Li 072; Yici Cai; Qiang Zhou 001 (ISCAS, 2021)

A Power Grids Electromigration Analysis with Via Array Using Current-Tracing Model. - Jing Wang 224; Yici Cai; Qiang Zhou 001 (ISCAS, 2021)

A game theory approach for RTL security verification resources allocation. - Haoyi Wang; Yici Cai; Qiang Zhou 001 (CCF Trans. High Perform. Comput., 2021)

Object Detection Made Simpler by Eliminating Heuristic NMS. - Qiang Zhou 001; Chaohui Yu; Chunhua Shen; Zhibin Wang 004; Hao Li 030 (CoRR, 2021)

Temperature-Aware Electromigration Analysis with Current-Tracking in Power Grid Networks. - Jing Wang 224; Yici Cai; Qiang Zhou 001 (J. Comput. Sci. Technol., 2021)

Placement and Routing Methods Considering Shape Constraints of JTL for RSFQ Circuits. - Jianwang Zhai; Yici Cai; Qiang Zhou 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A circuit protection method based on minterm perturbation. - Shiling Luo; Wenchao Gao; Le Huang; Qiang Zhou 001 (CIS, 2022)

TransMarker: A Pure Vision Transformer for Facial Landmark Detection. - Wenyan Wu 005; Yici Cai; Qiang Zhou 001 (ICPR, 2022)

MimCo: Masked Image Modeling Pre-training with Contrastive Teacher. - Qiang Zhou 001; Chaohui Yu; Hao Luo 004; Zhibin Wang 004; Hao Li 030 (ACM Multimedia, 2022)

Point RCNN: An Angle-Free Framework for Rotated Object Detection. - Qiang Zhou 001; Chaohui Yu; Zhibin Wang 004; Hao Li 030 (CoRR, 2022)

Intelligent and kernelized placement: A survey. - Rui Hao; Yici Cai; Qiang Zhou 001 (Integr., 2022)

A survey on machine learning-based routing for VLSI physical design. - Lin Li 072; Yici Cai; Qiang Zhou 001 (Integr., 2022)

Point RCNN: An Angle-Free Framework for Rotated Object Detection. - Qiang Zhou 001; Chaohui Yu (Remote. Sens., 2022)

Point-Teaching: Weakly Semi-supervised Object Detection with Point Annotations. - Yongtao Ge; Qiang Zhou 001; Xinlong Wang; Chunhua Shen; Zhibin Wang 004; Hao Li 030 (AAAI, 2023)

Static Probability Analysis Guided RTL Hardware Trojan Test Generation. - Haoyi Wang; Qiang Zhou 001; Yici Cai (ASP-DAC, 2023)

Foundation Model Drives Weakly Incremental Learning for Semantic Segmentation. - Chaohui Yu; Qiang Zhou 001; Jingliang Li; Jianlong Yuan; Zhibin Wang 004; Fan Wang 019 (CVPR, 2023)

D2Q-DETR: Decoupling and Dynamic Queries for Oriented Object Detection with Transformers. - Qiang Zhou 001; Chaohui Yu; Zhibin Wang 004; Fan Wang 019 (ICASSP, 2023)

LMSeg: Language-guided Multi-dataset Segmentation. - Qiang Zhou 001; Yuang Liu; Chaohui Yu; Jingliang Li; Zhibin Wang 004; Fan Wang 019 (ICLR, 2023)

Patch-level Contrastive Learning via Positional Query for Visual Pre-training. - Shaofeng Zhang; Qiang Zhou 001; Zhibin Wang 004; Fan Wang 019; Junchi Yan (ICML, 2023)

Points-to-3D: Bridging the Gap between Sparse Points and Shape-Controllable Text-to-3D Generation. - Chaohui Yu; Qiang Zhou 001; Jingliang Li; Zhe Zhang 049; Zhibin Wang 004; Fan Wang 019 (ACM Multimedia, 2023)

D2Q-DETR: Decoupling and Dynamic Queries for Oriented Object Detection with Transformers. - Qiang Zhou 001; Chaohui Yu; Zhibin Wang 004; Fan Wang 019 (CoRR, 2023)

Dynamic Token-Pass Transformers for Semantic Segmentation. - Yuang Liu; Qiang Zhou 001; Jing Wang 224; Fan Wang 019; Jun Wang 006; Wei Zhang 056 (CoRR, 2023)

ES-MVSNet: Efficient Framework for End-to-end Self-supervised Multi-View Stereo. - Qiang Zhou 001; Chaohui Yu; Jingliang Li; Yuang Liu; Jing Wang 224; Zhibin Wang 004 (CoRR, 2023)

RegionBLIP: A Unified Multi-modal Pre-training Framework for Holistic and Regional Comprehension. - Qiang Zhou 001; Chaohui Yu; Shaofeng Zhang; Sitong Wu; Zhibing Wang; Fan Wang 019 (CoRR, 2023)

Improved Neural Radiance Fields Using Pseudo-depth and Fusion. - Jingliang Li; Qiang Zhou 001; Chaohui Yu; Zhengda Lu; Jun Xiao 005; Zhibin Wang 004; Fan Wang 019 (CoRR, 2023)

ICPC: Instance-Conditioned Prompting with Contrastive Learning for Semantic Segmentation. - Chaohui Yu; Qiang Zhou 001; Zhibin Wang 004; Fan Wang 019 (CoRR, 2023)

InfMLLM: A Unified Framework for Visual-Language Tasks. - Qiang Zhou 001; Zhibin Wang 004; Wei Chu; Yinghui Xu; Hao Li 030; Yuan Qi 001 (CoRR, 2023)

McPAT-Calib: A RISC-V BOOM Microarchitecture Power Modeling Framework. - Jianwang Zhai; Chen Bai; Binwu Zhu; Yici Cai; Qiang Zhou 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Object Detection Made Simpler by Eliminating Heuristic NMS. - Qiang Zhou 001; Chaohui Yu (IEEE Trans. Multim., 2023)

An Empirical Study and Analysis of Text-to-Image Generation Using Large Language Model-Powered Textual Representation. - Zhiyu Tan; Mengping Yang; Luozheng Qin; Hao Yang; Ye Qian; Qiang Zhou 001; Cheng Zhang 014; Hao Li 030 (ECCV (80), 2024)

DMT: Comprehensive Distillation with Multiple Self-Supervised Teachers. - Yuang Liu; Jing Wang 224; Qiang Zhou 001; Fan Wang 019; Jun Wang 006; Wei Zhang 056 (ICASSP, 2024)

Language-Guided Few-Shot Semantic Segmentation. - Jing Wang 224; Yuang Liu; Qiang Zhou 001; Fan Wang 019 (ICASSP, 2024)

Continuous-Multiple Image Outpainting in One-Step via Positional Query and A Diffusion-based Approach. - Shaofeng Zhang; Jinfa Huang; Qiang Zhou 001; Zhibin Wang 004; Fan Wang 019; Jiebo Luo 001; Junchi Yan (ICLR, 2024)

Multimodal LLM Enhanced Cross-lingual Cross-modal Retrieval. - Yabing Wang; Le Wang 003; Qiang Zhou 001; Zhibin Wang 004; Hao Li 030; Gang Hua 001; Wei Tang 016 (ACM Multimedia, 2024)

Dynamic Token-Pass Transformers for Semantic Segmentation. - Yuang Liu; Qiang Zhou 001; Jing Wang 224; Zhibin Wang 004; Fan Wang 019; Jun Wang 006; Wei Zhang 056 (WACV, 2024)

CR2PQ: Continuous Relative Rotary Positional Query for Dense Visual Representation Learning. - Shaofeng Zhang; Qiang Zhou 001; Sitong Wu; Haoru Tan; Zhibin Wang 004; Jinfa Huang; Junchi Yan (ICLR, 2025)

Few-Shot Semantic Segmentation on Remote Sensing Images With Learnable Prototype. - Jing Wang 224; Yuang Liu; Qiang Zhou 001; Zhibin Wang 004; Fan Wang 019 (IEEE Trans. Geosci. Remote. Sens., 2025)

Raccoon: Multi-stage Diffusion Training with Coarse-to-Fine Curating Videos. - Zhiyu Tan; Junyan Wang 001; Hao Yang; Luozheng Qin; Hesen Chen; Qiang Zhou 001; Hao Li 030 (CoRR, 2025)