An Object-Oriented Design Process for System-on-Chip Using UML. - Tsuneo Nakata; Akio Matsuda; Minoru Shoji; Shinya Kuwamura; Qiang Zhu 005 (ISSS, 2002)

System-on-chip validation using UML and CWL. - Qiang Zhu 005; Ryosuke Oishi; Takashi Hasegawa; Tsuneo Nakata (CODES+ISSS, 2004)

System-on-Chip Verification Process Using UML. - Qiang Zhu 005; Tsuneo Nakata; Masataka Mine; Kenichiro Kuroki; Yoichi Endo; Takashi Hasegawa (UML Satellite Activities, 2004)

Integrating UML into SoC Design Process. - Qiang Zhu 005; Ryosuke Oishi; Takashi Hasegawa; Tsuneo Nakata (DATE, 2005)

Incremental high-level synthesis. - Luciano Lavagno; Alex Kondratyev; Yosinori Watanabe; Qiang Zhu 005; Mototsugu Fujii; Mitsuru Tatesawa; Noriyasu Nakayama (ASP-DAC, 2010)

Physically aware high level synthesis design flow. - Masato Tatsuoka; Ryosuke Watanabe; Tatsushi Otsuka; Takashi Hasegawa; Qiang Zhu 005; Ryosuke Okamura; Xingri Li; Tsuyoshi Takabatake (DAC, 2015)

High quality IP design using high-level synthesis design flow. - Qiang Zhu 005; Masato Tatsuoka (ASP-DAC, 2016)