A Stream System-on-Chip Architecture for High Speed Target Recognition Based on Biologic Vision. - Nan Wu 003; Qianming Yang; Mei Wen; Yi He 008; Changqing Xun; Chunyuan Zhang (Asia-Pacific Computer Systems Architecture Conference, 2007)

FT64: Scientific Computing with Streams. - Mei Wen; Nan Wu 003; Chunyuan Zhang; Wei Wu; Qianming Yang; Changqing Xun (HiPC, 2007)

FPGA-based Equivalent Simulation Technology (FEST) for clustered stream architecture. - Yi He 008; Ju Ren 002; Qianming Yang; Mei Wen; Nan Wu 003; Chunyuan Zhang (ACSAC, 2008)

On-Chip Memory System Optimization Design for the FT64 Scientific Stream Accelerator. - Mei Wen; Nan Wu 003; Chunyuan Zhang; Qianming Yang; Ju Ren 002; Yi He 008; Wei Wu; Jun Chai; Maolin Guan; Changqing Xun (IEEE Micro, 2008)

SAT: A Stream Architecture Template for Embedded Applications. - Qianming Yang; Nan Wu 003; Mei Wen; Yi He 008; Huayou Su; Chunyuan Zhang (CIT, 2010)

Software Managed Instruction Scratchpad Memory Optimization in Stream Architecture Based on Hot Code Analysis of Kernels. - Yi He 008; Ju Ren 002; Mei Wen; Qianming Yang; Nan Wu 003; Chunyuan Zhang (DSD, 2010)

Tiled Multi-Core Stream Architecture. - Nan Wu 003; Qianming Yang; Mei Wen; Yi He 008; Ju Ren 002; Maolin Guan; Chunyuan Zhang (Trans. High Perform. Embed. Archit. Compil., 2011)

The masala machine: accelerating thread-intensive and explicit memory management programs with dynamically reconfigurable FPGAs (abstract only). - Mei Wen; Nan Wu 003; Qianming Yang; Chunyuan Zhang; Liang Zhao (FPGA, 2012)

Fully Distributed On-chip Instruction Memory Design for Stream Architecture Based on Field-Divided VLIW Compression. - Yi He 008; Maolin Guan; Chunyuan Zhang; Tian Tian; Qianming Yang (HPCC-ICESS, 2012)

Simulating Cardiac Electrophysiology in the Era of GPU-Cluster Computing. - Jun Chai; Mei Wen; Nan Wu 003; Dafei Huang; Jing Yang; Xing Cai; Chunyuan Zhang; Qianming Yang (IEICE Trans. Inf. Syst., 2013)

SIR: A Secure Identifier-Based Inter-Domain Routing for Identifier/Locator Split Network. - Yaping Liu; Zhihong Liu; Baosheng Wang; Qianming Yang (IEICE Trans. Commun., 2013)

Accelerating thread-intensive and explicit memory management programs with dynamic partial reconfiguration. - Qianming Yang; Mei Wen; Nan Wu 003; Chunyuan Zhang (J. Supercomput., 2013)

Unified Virtual Memory Support for Deep CNN Accelerator on SoC FPGA. - Tao Xiao; Yuran Qiao; Junzhong Shen; Qianming Yang; Mei Wen (ICA3PP (1), 2015)

Enabling a Uniform OpenCL Device View for Heterogeneous Platforms. - Dafei Huang; Changqing Xun; Nan Wu 003; Mei Wen; Chunyuan Zhang; Xing Cai; Qianming Yang (IEICE Trans. Inf. Syst., 2015)

Optimizing OpenCL Implementation of Deep Convolutional Neural Network on FPGA. - Yuran Qiao; Junzhong Shen; Dafei Huang; Qianming Yang; Mei Wen; Chunyuan Zhang (NPC, 2017)

FPGA-accelerated deep convolutional neural networks for high throughput and energy efficiency. - Yuran Qiao; Junzhong Shen; Tao Xiao; Qianming Yang; Mei Wen; Chunyuan Zhang (Concurr. Comput. Pract. Exp., 2017)

Poster Abstract: A Template-based Framework for Generating Network Processor in FPGA. - Zhuang Cao; Huayou Su; Qianming Yang; Mei Wen; Chunyuan Zhang (INFOCOM Workshops, 2019)

P4 to FPGA-A Fast Approach for Generating Efficient Network Processors. - Zhuang Cao; Huayou Su; Qianming Yang; Junzhong Shen; Mei Wen; Chunyuan Zhang (IEEE Access, 2020)

Efficient Multiple-Precision and Mixed-Precision Floating-Point Fused Multiply-Accumulate Unit for HPC and AI Applications. - Hongbing Tan; Run Yan; Ling Yang 008; Libo Huang; Liquan Xiao; Qianming Yang (ICA3PP, 2022)

Low-Cost Multiple-Precision Multiplication Unit Design For Deep Learning. - Jing Zhang; Libo Huang; Hongbing Tan; Ling Yang 008; Zhong Zheng; Qianming Yang (ACM Great Lakes Symposium on VLSI, 2023)

A Low-Cost Floating-Point Dot-Product-Dual-Accumulate Architecture for HPC-Enabled AI. - Hongbing Tan; Libo Huang; Zhong Zheng; Hui Guo 004; Qianming Yang; Li Shen 007; Gang Chen 023; Liquan Xiao; Nong Xiao 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)