An Asynchronous RISC-V Processor Utilizing a Chisel-Based Desynchronization Flow. - Haoyang Huang; Jilin Zhang; Dexuan Huo; Qibang Sun; Woogeun Rhee; Hong Chen 002 (ISCAS, 2025)

Analysis and Design of Bias-Current-Free Hybrid Phase-Locked Loops with Multi-Phase Time-Interleaved Phase Detector. - Qibang Sun; Liqun Feng; Woogeun Rhee; Zhihua Wang (ISCAS, 2025)