DSI: Distributed Service Integration for Service Grid. - Guangwen Yang; ShuMing Shi 003; Dingxing Wang; Qifeng Huang; Xuezheng Liu (J. Comput. Sci. Technol., 2003)

WS-based workflow description language for message passing. - Yan Huang; Qifeng Huang (CCGRID, 2005)

Application of a robotic system with mobile manipulator and vision positioning. - Xuesong Shao; Jian Liu; Qing Xu; Qifeng Huang; Wei Xiao; Wei Wang; Chunlong Xing (AIM, 2015)

Path scheduling for multi-AGV system based on two-staged traffic scheduling scheme and genetic algorithm. - Jian Liu; Zhongdong Wang; Qing Xu; Qifeng Huang (J. Comput. Methods Sci. Eng., 2015)

Graph embedding and its application in defect detection system. - Qifeng Huang; Aixia Zheng; Xuesong Shao; Xiaoquan Lu; Meimei Duan (SPAC, 2017)

A 16b 5MS/s 93.7dB-SNDR SAR ADC with a Split Sampling Technique and SRM-Assisted Self-Calibration. - Qifeng Huang; Siji Huang; Yanhang Chen; Yifei Fan; Jie Yuan (CICC, 2024)

An Efficient 1.4-GS/s 10-bit Timing-Skew-Free Time-Interleaved SAR ADC With a Centralized Sampling Frontend. - Siji Huang; Debajit Basak; Yanhang Chen; Qifeng Huang; Yifei Fan; Jie Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 16-bit 4-MS/s SAR ADC With Dual-Segmental Bit Weight Self-Calibration. - Yanhang Chen; Qifeng Huang; Yifei Fan; Qiwei Zhao; Siji Huang; Jie Yuan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An 8-MS/s 16-bit SAR ADC With Symmetric Complementary Switching and Split Passive Reference Segmentation in 180-nm Process. - Siji Huang; Qifeng Huang; Yifei Fan; Qiwei Zhao; Yanhang Chen; Yihan Zhang 002; Jie Yuan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

An Injection-Locked and Sub-Sampling Clock Multiplier With a Two-Step SC DAC Achieving 2.67% Jitter Variation. - Qifeng Huang; Siji Huang; Yanhang Chen; Yifei Fan; Jie Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2024)

The Error Analysis of Bit Weight Self-Calibration Methods for High-Resolution SAR ADCs. - Yanhang Chen; Siji Huang; Qifeng Huang; Yifei Fan; Jie Yuan (IEEE Trans. Very Large Scale Integr. Syst., 2024)

A 16-bit 1-MS/s SAR ADC With Asynchronous LSB Averaging Achieving 95.1-dB SNDR and 98.1-dB DR. - Qiwei Zhao; Qifeng Huang; Yanhang Chen; Yifei Fan; Siji Huang; Jie Yuan (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A Voltage-Assist 16-Channel Electrochemical Biosensor With Linearity Compensation. - Yifei Fan; Dongmin Shi; Yanhang Chen; Qifeng Huang; Siji Huang; Qiwei Zhao; Saqib Mohamad; Jie Yuan (IEEE Trans. Biomed. Circuits Syst., 2025)

A 5-MS/s 16-bit Low-Noise and Low-Power Split Sampling SAR ADC With Eased Driving Burden. - Qifeng Huang; Siji Huang; Yanhang Chen; Yifei Fan; Qiwei Zhao; Jie Yuan (IEEE J. Solid State Circuits, 2025)