Qijing Huang

Orcid: 0000-0001-9084-8520

Affiliations:
  • University of California, Berkeley, CA, USA
  • University of Toronto, ON, Canada (former)


According to our database1, Qijing Huang authored at least 25 papers between 2013 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

On csauthors.net:

Bibliography

2023
Full Stack Optimization of Transformer Inference: a Survey.
CoRR, 2023

DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

2022
Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design.
Proceedings of the International IEEE Symposium on Performance Analysis of Systems and Software, 2022

2021
CoSA: Scheduling by Constrained Optimization for Spatial Accelerators.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

HAWQ-V3: Dyadic Neural Network Quantization.
Proceedings of the 38th International Conference on Machine Learning, 2021

CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs.
Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference.
Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

2020
HAWQV3: Dyadic Neural Network Quantization.
CoRR, 2020

CoDeNet: Algorithm-hardware Co-design for Deformable Convolution.
CoRR, 2020

ProTuner: Tuning Programs with Monte Carlo Tree Search.
CoRR, 2020

BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning.
Proceedings of Machine Learning and Systems 2020, 2020

AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud.
IEEE Micro, 2019

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning.
CoRR, 2019

Algorithm-hardware Co-design for Deformable Convolution.
Proceedings of the Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing, 2019

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration.
Proceedings of the International Conference on Computer-Aided Design, 2019

FPGA Accelerated INDEL Realignment in the Cloud.
Proceedings of the 25th IEEE International Symposium on High Performance Computer Architecture, 2019

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim.
Proceedings of the 2nd Workshop on Energy Efficient Machine Learning and Cognitive Computing for Embedded Applications, 2019

2017
Synthesis of program binaries into FPGA accelerators with runtime dependence validation.
Proceedings of the International Conference on Field Programmable Technology, 2017

2015
The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware.
ACM Trans. Reconfigurable Technol. Syst., 2015

2013
The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

From software to accelerators with LegUp high-level synthesis.
Proceedings of the International Conference on Compilers, 2013


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