From software to accelerators with LegUp high-level synthesis. - Andrew Canis; Jongsok Choi; Blair Fort; Ruolong Lian; Qijing Huang 001; Nazanin Calagar; Marcel Gort; Jia Jun Qin; Mark Aldham; Tomasz S. Czajkowski; Stephen Brown 003; Jason Helge Anderson (CASES, 2013)

The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Stephen Brown 003; Jason Helge Anderson (FCCM, 2013)

The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware. - Qijing Huang 001; Ruolong Lian; Andrew Canis; Jongsok Choi; Ryan Xi; Nazanin Calagar; Stephen Brown 003; Jason Helge Anderson (ACM Trans. Reconfigurable Technol. Syst., 2015)

Synthesis of program binaries into FPGA accelerators with runtime dependence validation. - Shaoyi Cheng; Qijing Huang 001; John Wawrzynek (FPT, 2017)

Integrating NVIDIA Deep Learning Accelerator (NVDLA) with RISC-V SoC on FireSim. - Farzad Farshchi; Qijing Huang 001; Heechul Yun (EMC2@HPCA/CVPR/ISCA, 2019)

AutoPhase: Compiler Phase-Ordering for HLS with Deep Reinforcement Learning. - Qijing Huang 001; Ameer Haj-Ali; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (FCCM, 2019)

Synetgy: Algorithm-hardware Co-design for ConvNet Accelerators on Embedded FPGAs. - Yifan Yang; Qijing Huang 001; Bichen Wu; Tianjun Zhang; Liang Ma 003; Giulio Gambardella; Michaela Blott; Luciano Lavagno; Kees A. Vissers; John Wawrzynek; Kurt Keutzer (FPGA, 2019)

FPGA Accelerated INDEL Realignment in the Cloud. - Lisa Wu 001; David Bruns-Smith; Frank A. Nothaft; Qijing Huang 001; Sagar Karandikar; Johnny Le; Andrew Lin; Howard Mao; Brendan Sweeney; Krste Asanovic; David A. Patterson 001; Anthony D. Joseph (HPCA, 2019)

Centrifuge: Evaluating full-system HLS-generated heterogenous-accelerator SoCs using FPGA-Acceleration. - Qijing Huang 001; Christopher Yarp; Sagar Karandikar; Nathan Pemberton; Benjamin Brock; Liang Ma 003; Guohao Dai; Robert Quitt; Krste Asanovic; John Wawrzynek (ICCAD, 2019)

Algorithm-hardware Co-design for Deformable Convolution. - Qijing Huang 001; Dequan Wang; Yizhao Gao 002; Yaohui Cai; Zhen Dong 003; Bichen Wu; Kurt Keutzer; John Wawrzynek (EMC2@NeurIPS, 2019)

AutoPhase: Compiler Phase-Ordering for High Level Synthesis with Deep Reinforcement Learning. - Ameer Haj Ali; Qijing Huang 001; William S. Moses; John Xiang; Ion Stoica; Krste Asanovic; John Wawrzynek (CoRR, 2019)

FireSim: FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud. - Sagar Karandikar; Howard Mao; Donggyu Kim; David Biancolin; Alon Amid; Dayeol Lee; Nathan Pemberton; Emmanuel Amaro; Colin Schmidt 001; Aditya Chopra; Qijing Huang 001; Kyle Kovacs; et al. (IEEE Micro, 2019)

AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs. - Keertana Settaluri; Ameer Haj-Ali; Qijing Huang 001; Kourosh Hakhamaneshi; Borivoje Nikolic (DATE, 2020)

AutoPhase: Juggling HLS Phase Orderings in Random Forests with Deep Reinforcement Learning. - Ameer Haj-Ali; Qijing (Jenny) Huang; William S. Moses; John Xiang; Krste Asanovic; John Wawrzynek; Ion Stoica (MLSys, 2020)

BRU: Bandwidth Regulation Unit for Real-Time Multicore Processors. - Farzad Farshchi; Qijing Huang 001; Heechul Yun (RTAS, 2020)

ProTuner: Tuning Programs with Monte Carlo Tree Search. - Ameer Haj-Ali; Hasan Genc; Qijing Huang 001; William S. Moses; John Wawrzynek; Krste Asanovic; Ion Stoica (CoRR, 2020)

CoDeNet: Algorithm-hardware Co-design for Deformable Convolution. - Zhen Dong 003; Dequan Wang; Qijing Huang 001; Yizhao Gao 002; Yaohui Cai; Bichen Wu; Kurt Keutzer; John Wawrzynek (CoRR, 2020)

HAWQV3: Dyadic Neural Network Quantization. - Zhewei Yao; Zhen Dong 003; Zhangcheng Zheng; Amir Gholami; Jiali Yu; Eric Tan; Leyuan Wang; Qijing Huang 001; Yida Wang; Michael W. Mahoney; Kurt Keutzer (CoRR, 2020)

HAO: Hardware-aware Neural Architecture Optimization for Efficient Inference. - Zhen Dong 003; Yizhao Gao 002; Qijing Huang 001; John Wawrzynek; Hayden K. H. So; Kurt Keutzer (FCCM, 2021)

CoDeNet: Efficient Deployment of Input-Adaptive Object Detection on Embedded FPGAs. - Qijing Huang 001; Dequan Wang; Zhen Dong 003; Yizhao Gao 002; Yaohui Cai; Tian Li; Bichen Wu; Kurt Keutzer; John Wawrzynek (FPGA, 2021)

HAWQ-V3: Dyadic Neural Network Quantization. - Zhewei Yao; Zhen Dong 003; Zhangcheng Zheng; Amir Gholami; Jiali Yu; Eric Tan; Leyuan Wang; Qijing Huang 001; Yida Wang; Michael W. Mahoney; Kurt Keutzer (ICML, 2021)

CoSA: Scheduling by Constrained Optimization for Spatial Accelerators. - Qijing Huang 001; Aravind Kalaiah; Minwoo Kang; James Demmel; Grace Dinh; John Wawrzynek; Thomas Norell; Yakun Sophia Shao (ISCA, 2021)

Co-design ofAlgorithms, Hardware, and Scheduling for Deep Learning Applications - Qijing Huang 001 (2021)

Learning A Continuous and Reconstructible Latent Space for Hardware Accelerator Design. - Qijing Huang 001; Charles Hong; John Wawrzynek; Mahesh Subedar; Yakun Sophia Shao (ISPASS, 2022)

DOSA: Differentiable Model-Based One-Loop Search for DNN Accelerators. - Charles Hong; Qijing Huang 001; Grace Dinh; Mahesh Subedar; Yakun Sophia Shao (MICRO, 2023)

Full Stack Optimization of Transformer Inference: a Survey. - Sehoon Kim 001; Coleman Hooper; Thanakul Wattanawong; Minwoo Kang; Ruohan Yan; Hasan Genc; Grace Dinh; Qijing Huang 001; Kurt Keutzer; Michael W. Mahoney; Yakun Sophia Shao; Amir Gholami (CoRR, 2023)

Mind the Gap: Attainable Data Movement and Operational Intensity Bounds for Tensor Algorithms. - Qijing Huang 001; Po-An Tsai; Joel S. Emer; Angshuman Parashar (ISCA, 2024)

DEMOTIC: A Differentiable Sampler for Multi-Level Digital Circuits. - Arash Ardakani; Minwoo Kang; Kevin He; Qijing Huang 001; Vighnesh M. Iyer; Suhong Moon; John Wawrzynek (ASP-DAC, 2025)

High-Throughput SAT Sampling. - Arash Ardakani; Minwoo Kang; Kevin He; Qijing Huang 001; John Wawrzynek (DATE, 2025)

ChipVQA: Benchmarking Visual Language Models for Chip Design. - Haoyu Yang; Qijing Huang 001; Nathaniel Ross Pinckney; Walker J. Turner; Wenfei Zhou; Yanqing Zhang 002; Chia-Tung Ho; Chen-Chia Chang; Haoxing Ren (DATE, 2025)