A new asynchronous delay-insensitive link based on a 1-of-4 LETS code. - Can Wang; Qin Wang 009; Jianfei Jiang 001 (ASICON, 2011)

Effective multi-standard macroblock prediction VLSI design for reconfigurable multimedia systems. - Yuliang Tao; Guanghui He; Weifeng He; Qin Wang 009; Jun Ma 012; Zhigang Mao (ISCAS, 2011)

A Case Study of CPNS Intelligence: Provenance Reasoning over Tracing Cross Contamination in Food Supply Chain. - Shunqing Yan; Yongxin Zhu 001; Qiannan Zhang; Qin Wang 009; Ming Ni; Guangwei Xie (ICDCS Workshops, 2012)

Group-Based Fast Mode Decision Algorithm for Intra Prediction in HEVC. - Shunqing Yan; Liang Hong; Weifeng He; Qin Wang 009 (SITIS, 2012)

TSVs-aware floorplanning for 3D integrated circuit. - Jieliang Lu; Qin Wang 009; Jing Xie 010; Zhigang Mao (ASICON, 2013)

Modeling and analysis of signal transmission with Through Silicon Via (TSV) noise coupling. - Zhenyang Chen; Qin Wang 009; Jing Xie 010; Jin Tian; Jianfei Jiang 001; Yufei Li; Wen Yin (ISCAS, 2013)

Fault detection and redundancy design for TSVs in 3D ICs. - Sai Hu; Qin Wang 009; Zheng Guo 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

A crosstalk avoidance scheme based on re-layout of signal TSV. - Jiayi Hu; Qin Wang 009; Jianfei Jiang 001; Jing Xie 010; Zhigang Mao (ASICON, 2015)

A Circuit Design of SMS4 against Chosen Plaintext Attack. - Jiachao Chen; Qin Wang 009; Zheng Guo 001; Junrong Liu; Haihua Gu (CIS, 2015)

A contactless testing methodology for pre-bond interposer. - Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao (MWSCAS, 2015)

Design optimization for capacitive-resistively driven on-chip global interconnect. - Jianfei Jiang 001; Weifeng He; Jizeng Wei; Qin Wang 009; Zhigang Mao (IEICE Electron. Express, 2015)

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects. - Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng; Qin Wang 009; Weifeng He (J. Circuits Syst. Comput., 2016)

A metastability-based true random number generator on FPGA. - Chaoyang Li 008; Qin Wang 009; Jianfei Jiang 001; Nin Guan (ASICON, 2017)

An on-chip circuit for timing measurement of SRAM IP. - Xianjie Long; Qin Wang 009; Jianfei Jiang 001; Nin Guan (ASICON, 2017)

Dynamic data split: A crosstalk suppression scheme in TSV-based 3D IC. - Qin Wang 009; Zhenyang Chen; Jianfei Jiang 001; Zheng Guo 001; Zhigang Mao (Integr., 2017)

Optimizing the data placement and transformation for multi-bank CGRA computing system. - Zhongyuan Zhao 004; Yantao Liu; Weiguang Sheng; Tushar Krishna; Qin Wang 009; Zhigang Mao (DATE, 2018)

MBSS: A General Paradigm for Static Schedule for Nested Loops with Dynamic Loop Boundary on CGRAs. - Shuai Xie; Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Zhigang Mao (ReConFig, 2018)

IBOM: An Integrated and Balanced On-Chip Memory for High Performance GPGPUs. - Jianfei Wang; Qin Wang 009; Li Jiang 002; Chao Li 009; Xiaoyao Liang; Naifeng Jing (IEEE Trans. Parallel Distributed Syst., 2018)

A New Approximate Multiplier Design for Digital Signal Processing. - Yue Zhao; Tong Li; Feng Dong; Qin Wang 009; Weifeng He; Jianfei Jiang 001 (ASICON, 2019)

A Rapid Scrubbing Technique for SEU Mitigation on SRAM-Based FPGAs. - Sijie Zheng; Hongjun You; Guanghui He; Qin Wang 009; Tao Si; Jianfei Jiang 001; Jing Jin 005; Naifeng Jing (ISCAS, 2019)

Lung Nodule Detection in CT Images Using a Raw Patch-Based Convolutional Neural Network. - Qin Wang 009; Fengyi Shen; Linyao Shen; Jia Huang; Weiguang Sheng (J. Digit. Imaging, 2019)

Scale Adaptive Proposal Network for Object Detection in Remote Sensing Images. - Shuo Zhang; Guanghui He; Hai-Bao Chen; Naifeng Jing; Qin Wang 009 (IEEE Geosci. Remote. Sens. Lett., 2019)

Energy-Efficient Nonvolatile SRAM Design Based on Resistive Switching Multi-Level Cells. - Yanan Sun 003; Jiawei Gu; Weifeng He; Qin Wang 009; Naifeng Jing; Zhigang Mao; Weikang Qian; Li Jiang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A Novel Resistive Memory-based Process-in-memory Architecture for Efficient Logic and Add Operations. - Taozhong Li; Qin Wang 009; Yongxin Zhu 001; Jianfei Jiang 001; Guanghui He; Jing Jin 005; Zhigang Mao; Naifeng Jing (ACM Trans. Design Autom. Electr. Syst., 2019)

A New Cellular-Based Redundant TSV Structure for Clustered Faults. - Qin Wang 009; Zechen Liu; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Frequency Attention Network: Blind Noise Removal for Real Images. - Hongcheng Mo; Jianfei Jiang 001; Qin Wang 009; Dong Yin; Pengyu Dong; Jingjun Tian (ACCV (2), 2020)

Enabling Resistive-RAM-based Activation Functions for Deep Neural Network Acceleration. - Zihan Zhang; Taozhong Li; Ning Guan; Qin Wang 009; Guanghui He; Weiguang Sheng; Zhigang Mao; Naifeng Jing (ACM Great Lakes Symposium on VLSI, 2020)

Decoupling the Multi-Rate Dataflow Execution in Coarse-Grained Reconfigurable Array. - Tu Hong; Ning Guan; Chen Yin; Qin Wang 009; Jianfei Jiang 001; Jing Jin 005; Guanghui He; Naifeng Jing (ISCAS, 2020)

Priority Branches for Ship Detection in Optical Remote Sensing Images. - Yijia Zhang; Weiguang Sheng; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao (Remote. Sens., 2020)

Towards Higher Performance and Robust Compilation for CGRA Modulo Scheduling. - Zhongyuan Zhao 004; Weiguang Sheng; Qin Wang 009; Wenzhi Yin; Pengfei Ye; Jinchao Li; Zhigang Mao (IEEE Trans. Parallel Distributed Syst., 2020)

A Mapping Method for Reconfigurable Array based on Decoupled DataFlow. - Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Zhigang Mao; Naifeng Jing (BigDataSecurity, 2021)

Subgraph Decoupling and Rescheduling for Increased Utilization in CGRA Architecture. - Chen Yin; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Guanghui He; Zhigang Mao; Naifeng Jing (DATE, 2021)

Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars. - Weiyi Liu; Yanan Sun 003; Weifeng He; Qin Wang 009 (ISCAS, 2021)

Fast FPGA-Based Emulation for ReRAM-Enabled Deep Neural Network Accelerator. - Yongquan Shi; Yongshuai Sun; Jianfei Jiang 001; Guanghui He; Qin Wang 009; Naifeng Jing (ISCAS, 2021)

Boosting ReRAM-based DNN by Row Activation Oversubscription. - Mengyu Guo; Zihan Zhang; Jianfei Jiang 001; Qin Wang 009; Naifeng Jing (ASP-DAC, 2022)

Hierarchical photoelectric hybrid packet switching network for high-performance computing. - Bingxi Pei; Shi Xu; Zhang Luo; Qin Wang 009; Mingche Lai; Wei-Feng He (JOCN, 2022)

A Low Coupling and Lightweight Algorithm for Ship Detection in Optical Remote Sensing Images. - Guochao Deng; Qin Wang 009; Jianfei Jiang 001; Qirun Hong; Naifeng Jing; Weiguang Sheng; Zhigang Mao (IEEE Geosci. Remote. Sens. Lett., 2022)

A Universal RRAM-Based DNN Accelerator With Programmable Crossbars Beyond MVM Operator. - Zihan Zhang; Jianfei Jiang 001; Yongxin Zhu 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Novel Architecture Design for Output Significance Aligned Flow with Adaptive Control in ReRAM-based Neural Network Accelerator. - Taozhong Li; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Yiran Chen 001 (ACM Trans. Design Autom. Electr. Syst., 2022)

An Efficient CNN Accelerator Using Inter-Frame Data Reuse of Videos on FPGAs. - Shengzhao Li; Qin Wang 009; Jianfei Jiang 001; Weiguang Sheng; Naifeng Jing; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

ReMap: Reorder Mapping for Multi-level Uneven Distribution on Sparse ReRAM Accelerator. - Zhuo Chen; Zihan Zhang; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009; Naifeng Jing (ASICON, 2023)

High-Performance Genomic Analysis Heterogeneous System Using OpenCL. - Jianing Gao; Lingyi Liu; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001 (ASICON, 2023)

An NoC-based CNN Accelerator for Edge Computing. - Jianing Gao; Qiming Shao; Fangyu Deng; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001 (ASICON, 2023)

An Efficient near-Bank Processing Architecture for Personalized Recommendation System. - Yuqing Yang; Weidong Yang; Qin Wang 009; Naifeng Jing; Jianfei Jiang 001; Zhigang Mao; Weiguang Sheng (ASP-DAC, 2023)

Pipeline Balancing for Integrated Mapping in High Performance Spatial Programmable Architecture. - Pengyu Liu 004; Zihan Zhang; Chen Yin; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (FPL, 2023)

ACET: An Adaptive Clock Scheme Exploiting Comprehensive Timing Slack for Reconfigurable Processors. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Weiguang Sheng; Ang Li; Qin Wang 009 (ICCD, 2023)

RTMDet-R2: An Improved Real-Time Rotated Object Detector. - Haifeng Xiang; Naifeng Jing; Jianfei Jiang 001; Hongbo Guo; Weiguang Sheng; Zhigang Mao; Qin Wang 009 (PRCV (12), 2023)

Exploiting bit sparsity in both activation and weight in neural networks accelerators. - Naifeng Jing; Zihan Zhang; Yongshuai Sun; Pengyu Liu 004; Liyan Chen; Qin Wang 009; Jianfei Jiang 001 (Integr., 2023)

A Reschedulable Dataflow-SIMD Execution for Increased Utilization in CGRA Cross-Domain Acceleration. - Chen Yin; Naifeng Jing; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars. - Yanan Sun 003; Zhi Li 058; Weiyi Liu; Weifeng He; Qin Wang 009; Zhigang Mao (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

A Unified Clock-Gated Error Correction Scheme With Three-Phase Latch-Based Pipeline for Energy-Efficient Wide Supply Voltage Range Router. - Bingxi Pei; Shi Xu; Zhang Luo; Qin Wang 009; Mingche Lai; Weifeng He (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Bridge-NDP: Achieving Efficient Communication-Computation Overlap in Near Data Processing with Bridge Architecture. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

SparGNN: Efficient Joint Feature-Model Sparsity Exploitation in Graph Neural Network Acceleration. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASPDAC, 2024)

Enabling Multiple Tensor-wise Operator Fusion for Transformer Models on Spatial Accelerators. - Lei Xu; Zhiwen Mo; Qin Wang 009; Jianfei Jiang 001; Naifeng Jing (DAC, 2024)

VDA: A Simple but Efficient Virtual-Channel-Based Deadlock Avoidance Scheme for Scalable Chiplet Networks. - Duo Yu; Ang Li; Naifeng Jing; Jianfei Jiang 001; Weiguang Sheng; Qin Wang 009 (ACM Great Lakes Symposium on VLSI, 2024)

A Low-Power and High-Accuracy Approximate Adder for Logarithmic Number System. - Wenhui Zhang; Xinkuang Geng; Qin Wang 009; Jie Han 001; Honglan Jiang (ACM Great Lakes Symposium on VLSI, 2024)

A 0.8-ps RMS Precision Period Jitter Measurement Circuit with Offset Reduction. - Lin Xie; Zizheng Dong; Jialei Sun; Sai Gao; Shuaipeng Li; Naifeng Jing; Qin Wang 009; Jianfei Jiang 001 (ISCAS, 2024)

An Architectural Error Metric for CNN-Oriented Approximate Multipliers. - Ao Liu; Jie Han 001; Qin Wang 009; Zhigang Mao; Honglan Jiang (CoRR, 2024)

A novel vehicle collision detection system: Integrating audio-visual fusion for enhanced performance. - Kunyue Li; Zhengji Zhao; Qixuan Cai; Qin Wang 009; Naifeng Jing; Zhigang Mao; Jianfei Jiang 001 (Expert Syst. Appl., 2024)

3A-ReRAM: Adaptive Activation Accumulation in ReRAM-Based CNN Accelerator. - Zihan Zhang; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

DeltaGNN: Accelerating Graph Neural Networks on Dynamic Graphs With Delta Updating. - Chen Yin; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

RecPIM: Efficient In-Memory Processing for Personalized Recommendation Inference Using Near-Bank Architecture. - Weidong Yang; Yuqing Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

A Comprehensive Dataflow-Mapping Optimization for Fully Pipelined Execution in Spatial Programmable Architecture. - Pengyu Liu 004; Ang Li; Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

MDNMP: Metapath-Driven Software-Hardware Co-Design for HGNN Acceleration with Near-Memory Processing. - Liyan Chen; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (ASP-DAC, 2025)

HEILP: An ILP-Based Scale Management Method for Homomorphic Encryption Compiler. - Weidong Yang; Shuya Ji; Jianfei Jiang 001; Naifeng Jing; Qin Wang 009; Zhigang Mao; Weiguang Sheng (DATE, 2025)

AsyncDIMM: Achieving Asynchronous Execution in DIMM-Based Near-Memory Processing. - Liyan Chen; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (HPCA, 2025)

Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density. - Dengfeng Wang; Weifeng He; Qin Wang 009; Hailong Jiao; Yanan Sun 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

A Hierarchical 3-D Physical Design Method for Ultralarge-Scale Logic-on-Memory CGRA Chip. - Zizheng Dong; Shuaipeng Li; Weijia Zhu; Ang Li; Qin Wang 009; Naifeng Jing; Weiguang Sheng; Jianfei Jiang 001; Zhigang Mao (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Bridge-NDP: Efficient Communication-Computation Overlap in Near Data Processing System. - Liyan Chen; Pengyu Liu 004; Dongxu Lyu; Jianfei Jiang 001; Qin Wang 009; Zhigang Mao; Naifeng Jing (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

MACS: A Multidomain Collaborative Adaptive Clock Scheme for Large-Scale Reconfigurable Dataflow Accelerators. - Shuya Ji; Weidong Yang; Jianfei Jiang 001; Naifeng Jing; Honglan Jiang; Zhigang Mao; Qin Wang 009 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)