Logic BIST Architecture for System-Level Test and Diagnosis. - Jun Qian; Xingang Wang; Qinfu Yang; Fei Zhuang; Junbo Jia; Xiangfeng Li; Yuan Zuo; Jayanth Mekkoth; Jinsong Liu; Hao-Jan Chao; Shianling Wu; Huafeng Yang; et al. (Asian Test Symposium, 2009)

Scan Test Data Volume Reduction for SoC Designs in EDT Environment. - Guoliang Li 004; Jun Qian; Yuan Zuo; Rui Li 084; Qinfu Yang (Asian Test Symposium, 2013)

Hybrid Hierarchical and Modular Tests for SoC Designs. - Guoliang Li 004; Jun Qian; Qinfu Yang; Yuan Zuo; Rui Li 084; Yu Huang 005; Mark Kassab; Janusz Rajski (NATW, 2015)

Industrial Case Studies of SoC Test Scheduling Optimization by Selecting Appropriate EDT Architectures. - Guoliang Li 004; Henry Zhao; Qinfu Yang; Jun Qian; Yu Huang 005 (ITC-Asia, 2018)

Access-Time Minimization in the IEEE 1687 Network Using Broadcast and Hardware Parallelism. - Zhanwei Zhong; Guoliang Li 004; Qinfu Yang; Krishnendu Chakrabarty (ITC, 2018)

Broadcast-based minimization of the overall access time for the IEEE 1687 network. - Zhanwei Zhong; Guoliang Li 004; Qinfu Yang; Jun Qian; Krishnendu Chakrabarty (VTS, 2018)

Access-Time Minimization for the IJTAG Network Using Data Broadcast and Hardware Parallelism. - Zhanwei Zhong; Guoliang Li 004; Qinfu Yang; Krishnendu Chakrabarty (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)