27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications. - Yejoong Kim; Wanyeong Jung; Inhee Lee 001; Qing Dong 001; Michael B. Henry; Dennis Sylvester; David T. Blaauw (ISSCC, 2014)

Racetrack converter: A low power and compact data converter using racetrack spintronic devices. - Qing Dong 001; Kaiyuan Yang 001; Laura Fick; David Fick; David T. Blaauw; Dennis Sylvester (ISCAS, 2015)

14.2 A physically unclonable function with BER-8 for robust chip authentication using oscillator collapse in 40nm CMOS. - Kaiyuan Yang 001; Qing Dong 001; David T. Blaauw; Dennis Sylvester (ISSCC, 2015)

A 23mW face recognition accelerator in 40nm CMOS with mostly-read 5T memory. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (VLSIC, 2015)

A2: Analog Malicious Hardware. - Kaiyuan Yang 001; Matthew Hicks; Qing Dong 001; Todd M. Austin; Dennis Sylvester (IEEE Symposium on Security and Privacy, 2016)

A 114-pW PMOS-only, trim-free voltage reference with 0.26% within-wafer inaccuracy for nW systems. - Qing Dong 001; Kaiyuan Yang 001; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2016)

A 1.02nW PMOS-only, trim-free current reference with 282ppm/°C from -40°C to 120°C and 1.6% within-wafer inaccuracy. - Qing Dong 001; Inhee Lee 001; Kaiyuan Yang 001; David T. Blaauw; Dennis Sylvester (ESSCIRC, 2017)

Rectified-linear and recurrent neural networks built with spin devices. - Qing Dong 001; Kaiyuan Yang 001; Laura Fick; David T. Blaauw; Dennis Sylvester (ISCAS, 2017)

14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligence. - Suyoung Bang; Jingcheng Wang; Ziyun Li; Cao Gao; Yejoong Kim; Qing Dong 001; Yen-Po Chen; Laura Fick; Xun Sun; Ronald G. Dreslinski; Trevor N. Mudge; Hun-Seok Kim; et al. (ISSCC, 2017)

11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodes. - Qing Dong 001; Yejoong Kim; Inhee Lee 001; Myungjoon Choi; Ziyun Li; Jingcheng Wang; Kaiyuan Yang 001; Yen-Po Chen; Junjie Dong; Minchang Cho; Gyouho Kim; Wei-Keng Chang; et al. (ISSCC, 2017)

3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigation. - Ziyun Li; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Shijia Yang; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (ISSCC, 2017)

8.3 A 553F2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instability. - Kaiyuan Yang 001; Qing Dong 001; David T. Blaauw; Dennis Sylvester (ISSCC, 2017)

9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependence. - Kaiyuan Yang 001; Qing Dong 001; Wanyeong Jung; Yiqun Zhang 002; Myungjoon Choi; David T. Blaauw; Dennis Sylvester (ISSCC, 2017)

Exploiting the analog properties of digital circuits for malicious hardware. - Kaiyuan Yang 001; Matthew Hicks; Qing Dong 001; Todd M. Austin; Dennis Sylvester (Commun. ACM, 2017)

A 23-mW Face Recognition Processor with Mostly-Read 5T Memory in 40-nm CMOS. - Dongsuk Jeon; Qing Dong 001; Yejoong Kim; Xiaolong Wang; Shuai Chen; Hao Yu 001; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2017)

Low-Power and Compact Analog-to-Digital Converter Using Spintronic Racetrack Memory Devices. - Qing Dong 001; Kaiyuan Yang 001; Laura Fick; David Fick; David T. Blaauw; Dennis Sylvester (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 1Mb 28nm STT-MRAM with 2.8ns read access time at 1.2V VDD using single-cap offset-cancelled sense amplifier and in-situ self-write-termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (ISSCC, 2018)

A 0.04MM316NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement. - Xiao Wu 002; Inhee Lee 001; Qing Dong 001; Kaiyuan Yang 001; Dongkwun Kim; Jingcheng Wang; Yimai Peng; Yiqun Zhang 002; Mehdi Saligane; Makoto Yasuda; Kazuyuki Kumeno; Fumitaka Ohno; et al. (VLSI Circuits, 2018)

An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration. - Mehdi Saligane; Jeongsup Lee; Qing Dong 001; Makoto Yasuda; Kazuyuki Kumeno; Fumitaka Ohno; Satoru Miyoshi; Masaru Kawaminami; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2018)

A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. - Kaiyuan Yang 001; Qing Dong 001; Zhehong Wang; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (VLSI Circuits, 2018)

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin. - Qing Dong 001; Supreet Jeloka; Mehdi Saligane; Yejoong Kim; Masaru Kawaminami; Akihiko Harada; Satoru Miyoshi; Makoto Yasuda; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2018)

A 1920 × 1080 30-frames/s 2.3 TOPS/W Stereo-Depth Processor for Energy-Efficient Autonomous Navigation of Micro Aerial Vehicles. - Ziyun Li; Qing Dong 001; Mehdi Saligane; Benjamin P. Kempke; Luyao Gong; Zhengya Zhang; Ronald G. Dreslinski; Dennis Sylvester; David T. Blaauw; Hun-Seok Kim (IEEE J. Solid State Circuits, 2018)

Recryptor: A Reconfigurable Cryptographic Cortex-M0 Processor With In-Memory and Near-Memory Computing for IoT Security. - Yiqun Zhang 002; Li Xu 006; Qing Dong 001; Jingcheng Wang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2018)

A 6.4pJ/Cycle Self-Tuning Cortex-M0 IoT Processor Based on Leakage-Ratio Measurement for Energy-Optimal Operation Across Wide-Range PVT Variation. - Jeongsup Lee; Yiqun Zhang 002; Qing Dong 001; Wootaek Lim; Mehdi Saligane; Yejoong Kim; Seokhyeon Jeong; Jongyup Lim; Makoto Yasuda; Satoru Miyoshi; Masaru Kawaminami; David T. Blaauw; et al. (ISSCC, 2019)

A 1-Mb 28-nm 1T1MTJ STT-MRAM With Single-Cap Offset-Cancelled Sense Amplifier and In Situ Self-Write-Termination. - Qing Dong 001; Zhehong Wang; Jongyup Lim; Yiqun Zhang 002; Mahmut E. Sinangil; Yi-Chun Shih; Yu-Der Chih; Tsung-Yung Jonathan Chang; David T. Blaauw; Dennis Sylvester (IEEE J. Solid State Circuits, 2019)

15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications. - Qing Dong 001; Mahmut E. Sinangil; Burak Erbagci; Dar Sun; Win-San Khwa; Hung-Jen Liao; Yih Wang; Jonathan Chang (ISSCC, 2020)

An All-Weights-on-Chip DNN Accelerator in 22nm ULL Featuring 24×1 Mb eRRAM. - Zhehong Wang; Ziyun Li; Li Xu 006; Qing Dong 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; David T. Blaauw (VLSI Circuits, 2020)

A Self-Tuning IoT Processor Using Leakage-Ratio Measurement for Energy-Optimal Operation. - Jeongsup Lee; Satoru Miyoshi; Masaru Kawaminami; David T. Blaauw; Dennis Sylvester; Yiqun Zhang 002; Qing Dong 001; Wootaek Lim; Mehdi Saligane; Yejoong Kim; Seokhyeon Jeong; Jongyup Lim; et al. (IEEE J. Solid State Circuits, 2020)

RRAM-DNN: An RRAM and Model-Compression Empowered All-Weights-On-Chip DNN Accelerator. - Ziyun Li; Zhehong Wang; Li Xu 006; Qing Dong 001; Bowen Liu 001; Chin-I Su; Wen-Ting Chu; George Tsou; Yu-Der Chih; Tsung-Yung Jonathan Chang; Dennis Sylvester; Hun-Seok Kim; et al. (IEEE J. Solid State Circuits, 2021)