Constraint-free analog placement with topological symmetry structure. - Qing Dong 002; Shigetoshi Nakatake (ASP-DAC, 2008)

STI stress aware placement optimization based on geometric programming. - Jing Li 072; Bo Yang 004; Xiaochuan Hu; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2009)

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming. - Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Structured Placement with Topological Regularity Evaluation. - Qing Dong 002; Shigetoshi Nakatake (IPSJ Trans. Syst. LSI Des. Methodol., 2009)

Structured analog circuit design and MOS transistor decomposition for high accuracy applications. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (ICCAD, 2010)

Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path. - Jing Li 072; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISCAS, 2010)

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs. - Kota Shinohara; Mihoko Hidaka; Jing Li 072; Qing Dong 002; Bo Yang 004; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2011)

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis. - Bo Liu 031; Qing Dong 002; Bo Yang 004; Jing Li 072; Shigetoshi Nakatake (ISQED, 2011)

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications. - Qing Dong 002; Bo Yang 004; Gong Chen 002; Jing Li 072; Shigetoshi Nakatake (ISQED, 2012)

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm. - Gong Chen 002; Bo Yang 004; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ACM Great Lakes Symposium on VLSI, 2013)

A comparator energy model considering shallow trench isolation stress by geometric programming. - Gong Chen 002; Yu Zhang; Bo Yang 004; Qing Dong 002; Shigetoshi Nakatake (ISQED, 2013)

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects. - Yu Zhang; Gong Chen 002; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (VLSI-SoC, 2013)

Structured Analog Circuit and Layout Design with Transistor Array. - Bo Yang 004; Qing Dong 002; Jing Li 072; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming. - Yu Zhang; Gong Chen 002; Bo Yang 004; Jing Li 072; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning. - Daijiro Murooka; Yu Zhang; Qing Dong 002; Shigetoshi Nakatake (ISVLSI, 2015)

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC. - Gong Chen 002; Yu Zhang; Qing Dong 002; Mingyu Li; Shigetoshi Nakatake (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015)

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout. - Gong Chen 002; Toru Fujimura; Qing Dong 002; Shigetoshi Nakatake; Bo Yang 004 (ACM Trans. Design Autom. Electr. Syst., 2016)