A -107dBe, 10kHz carrier offset 2-GHz DLL-based frequency synthesizer. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (CICC, 2003)

A 4-GB/S half-rate clock and data recovery circuit with a 3-stage VCO. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (Circuits, Signals, and Systems, 2005)

A Low Phase Noise Dll Clock Generator with a Programmable Dynamic Frequency Divider. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (CCECE, 2006)

An Anti-Harmonic Locking, DLL Frequency Multiplier with Low Phase Noise and Reduced Spur. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (CICC, 2006)

An eye detection technique for clock and data recovery applications. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (ISCAS, 2006)

A Timing Jitter Reduction Technique in a Cyclic Injection Clock Multiplier for Data Communication System. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (SoCC, 2006)

A Low-Phase Noise, Anti-Harmonic Programmable DLL Frequency Multiplier With Period Error Compensation for Spur Reduction. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

A 4GHz Low Complexity ADPLL-based Frequency Synthesizer in 90nm CMOS. - Jingcheng Zhuang; Qingjin Du; Tad A. Kwasniewski (CICC, 2007)

A Low-Power, Fast Acquisition, Data Recovery Circuit With Digital Threshold Decision for SFI-5 Application. - Qingjin Du; Jingcheng Zhuang; Tad A. Kwasniewski (IEEE Trans. Very Large Scale Integr. Syst., 2009)