ITester: A FPGA based high performance traffic replay tool. - Fuxing Zhang; Yingke Xie; Junjie Liu; Layong Luo; Qingsong Ning; Xiaolong Wu (FPL, 2012)

Building a Flexible and Scalable Virtual Hardware Data Plane. - Junjie Liu; Yingke Xie; Gaogang Xie; Layong Luo; Fuxing Zhang; Xiaolong Wu; Qingsong Ning; Hongtao Guan (Networking (1), 2012)

FAERY: An FPGA-accelerated Embedding-based Retrieval System. - Chaoliang Zeng; Layong Luo; Qingsong Ning; Yaodong Han; Yuhang Jiang; Ding Tang; Zilong Wang 007; Kai Chen 005; Chuanxiong Guo (OSDI, 2022)

SRNIC: A Scalable Architecture for RDMA NICs. - Zilong Wang 007; Layong Luo; Qingsong Ning; Chaoliang Zeng; Wenxue Li; Xinchen Wan; Peng Xie; Tao Feng; Ke Cheng; Xiongfei Geng; Tianhao Wang 025; Weicheng Ling; et al. (NSDI, 2023)

Fast, Scalable, and Accurate Rate Limiter for RDMA NICs. - Zilong Wang 007; Xinchen Wan; Luyang Li; Yijun Sun; Peng Xie; Xin Wei; Qingsong Ning; Junxue Zhang 001; Kai Chen 005 (SIGCOMM, 2024)

Harmonia: A Unified Framework for Heterogeneous FPGA Acceleration in the Cloud. - Luyang Li; Heng Pan; Xinchen Wan; Kai Lv; Zilong Wang 007; Qian Zhao 001; Feng Ning; Qingsong Ning; Shideng Zhang; Zhenyu Li 001; Layong Luo; Gaogang Xie (ASPLOS (2), 2025)

A Generic and Efficient Communication Framework for Message-Level In-Network Computing. - Xinchen Wan; Luyang Li; Han Tian; Xudong Liao; Xinyang Huang; Chaoliang Zeng; Zilong Wang 007; Xinyu Yang; Ke Cheng; Qingsong Ning; Guyue Liu; Layong Luo; et al. (INFOCOM, 2025)