Work-in-Process: Error-Compensation-Based Energy-Efficient MAC Unit for CNNs. - Xingyu Xu 008; Qingwen Wei; Yang Zhang 132; Hao Cai 001; Bo Liu 019 (CASES, 2023)

An Energy-Efficient MAC Design with Error Compensation Using Hybrid Approximate Logic Synthesis. - Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ICTA, 2023)

FDCA: Fine-grained Digital-CIM based CNN Accelerator with Hybrid Quantization and Weight-Stationary Dataflow. - Bo Liu 019; Qingwen Wei; Yang Zhang 132; Xingyu Xu 008; Zihan Zou; Xinxiang Huang; Xin Si; Hao Cai 001 (DAC, 2024)

ChipExpert: The Open-Source Integrated-Circuit-Design-Specific Large Language Model. - Ning Xu 009; Zhaoyang Zhang; Lei Qi 001; Wensuo Wang; Chao Zhang; Zihao Ren; Huaiyuan Zhang; Xin Cheng; Yanqi Zhang; Zhichao Liu; Qingwen Wei; Shiyang Wu; et al. (CoRR, 2024)

Timing Error Tolerant CNN Accelerator With Layerwise Approximate Multiplication. - Bo Liu 019; Na Xie; Qingwen Wei; Guang Yang 036; Chonghang Xie; Weiqiang Liu 001; Hao Cai 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

SUArch: Accelerating Layer-wise N: M Sparse Pattern with a Unified Architecture for Deep-learning Edge Device. - Xilong Kang; Qingwen Wei; Ningyuan Li 004; Xingyu Xu 008; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

TWDP: A Vision Transformer Accelerator with Token-Weight Dual-Pruning Strategy for Edge Device Deployment. - Guang Yang 036; Xinming Yan; Hui Kou; Zihan Zou; Qingwen Wei; Hao Cai 001; Bo Liu 019 (ASP-DAC, 2025)

A 52.03TOPS/W DCIM-Based Accelerator with FlashAttention and Sparsity-Aware Alignment for LLMs. - Bo Liu 019; Xingyu Xu 008; Yang Zhang 132; Xilong Kang; Qingwen Wei; Zihan Zou; Jun Yang 006; Hao Cai 001; Xin Si (CICC, 2025)

A Layer-wise N: M Sparsity Aware Transformer Accelerator leveraging Temporal Locality with Butterfly Network. - Qinfan Wang; Yuan Song; Xilong Kang; Qingwen Wei; Cai Hao; Bo Liu (ISCAS, 2025)