A High-speed 32-bit Signed/Unsigned Pipelined Multiplier. - Qingzheng Li; Guixuan Liang; Amine Bermak (DELTA, 2010)

An FPGA-Based Neural Network Overlay for ADAS Supporting Multi-Model and Multi-Mode. - Jiaxi Zhang 001; Tao Yang 031; Qingzheng Li; Bo Zhou; Yang Yang; Guojie Luo; Jianping Shi (ISCAS, 2021)

BISWSRBS: A Winograd-based CNN Accelerator with a Fine-grained Regular Sparsity Pattern and Mixed Precision Quantization. - Tao Yang 031; Zhezhi He; Tengchuan Kou; Qingzheng Li; Qi Han; Haibao Yu; Fangxin Liu; Yun Liang 001; Li Jiang 002 (ACM Trans. Reconfigurable Technol. Syst., 2021)

A Novel Hybrid Power Supply System with Fast Response for Microprocessor. - Jiarui Wu; Xu Yang 012; Xingwei Huang; Qingzheng Li; Kangping Wang; Wenjie Chen (IEEE Trans. Ind. Electron., 2024)