Design considerations for low-power analog front ends in full-duplex 10GBASE-T transceivers. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (CICC, 2014)

8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. - Jan R. Westra; Jan Mulder; Yi Ke; Davide Vecchi; Xiaodong Liu; Erol Arslan; Jiansong Wan; Qiongna Zhang; Sijia Wang; Frank M. L. van der Goes; Klaas Bult (ISSCC, 2014)

26.3 An 800MS/S 10b/13b receiver for 10GBASE-T Ethernet in 28nm CMOS. - Jan Mulder; Davide Vecchi; Yi Ke; Stefano Bozzola; Mark Core; Nitz Saputra; Qiongna Zhang; Jeff Riley; Han Yan; Mattia Introini; Sijia Wang; Christopher M. Ward; et al. (ISSCC, 2015)