Logic-DRAM Co-Design to Exploit the Efficient Repair Technique for Stacked DRAM. - Minjie Lv; Hongbin Sun 001; Qiwei Ren; Bing Yu; Jingmin Xin; Nanning Zheng 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A two-port SRAM using a single-port cell array with a self-timed write-after-read control scheme to save 47% area & 63% standby power. - Fujun Bai; Baoyu Xiong; Xiaofei Xue; Weizhe Song; Baofeng Wu; Ni Fu; Bing Yu; Huifu Duan; Xiaowei Han; Alessandro Minzoni; Qiwei Ren (ASICON, 2017)

A 0.13μm 64Mb HfOx ReRAM using configurable ramped voltage write and low read-disturb sensing techniques for reliability improvement. - Xiaowei Han; Qian Jia; Hongbin Sun 001; Longfei Wang; Huaqiang Wu; Yimao Cai; Feng Zhang 014; Yongyi Xie; Fangxu Dong; Xiaoguang Wang 015; Xiaofei Xue; Li Pang; et al. (CICC, 2017)

A 1596GB/s 48Gb Embedded DRAM 384-Core SoC with Hybrid Bonding Integration. - Xiping Jiang; Fengguo Zuo; Song Wang; Xiaofeng Zhou; Bing Yu; Yubing Wang; Qi Liu; Ming Liu; Yi Kang; Qiwei Ren (A-SSCC, 2021)

184QPS/W 64Mb/mm23D Logic-to-DRAM Hybrid Bonding with Process-Near-Memory Engine for Recommendation System. - Dimin Niu; Shuangchen Li; Yuhao Wang 002; Wei Han; Zhe Zhang 006; Yijin Guan; Tianchan Guan; Fei Sun; Fei Xue; Lide Duan; Yuanwei Fang; Hongzhong Zheng; et al. (ISSCC, 2022)

Low Overhead Pilot Design for Channel Estimation in MIMO-OTFS Systems. - Qiwei Ren; Qiyishu Li; Zhikun Xu; Zhengang Pan (ICCC Workshops, 2023)

A 135 GBps/Gbit 0.66 pJ/bit Stacked Embedded DRAM with Multilayer Arrays by Fine Pitch Hybrid Bonding and Mini-TSV. - Song Wang; Bing Yu; Wenwu Xiao; Fujun Bai; Xiaodong Long; Liang Bai; Xuerong Jia; Fengguo Zuo; Jie Tan; Yixin Guo; Peng Sun; Jun Zhou; et al. (VLSI Technology and Circuits, 2023)

A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. - Fujun Bai; Song Wang; Xuerong Jia; Yixin Guo; Bing Yu; Hang Wang; Cong Lai; Qiwei Ren; Hongbin Sun 001 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Hf0.5Zr0.5O2 1T-1C FeRAM arrays with excellent endurance performance for embedded memory. - Wenwu Xiao; Yue Peng; Yan Liu; Huifu Duan; Fujun Bai; Bing Yu; Qiwei Ren; Xiao Yu; Genquan Han (Sci. China Inf. Sci., 2023)