Software-Hardware Co-Optimization on Partial-Sum Problem for PIM-based Neural Network Accelerator. - Qizhe Wu; Linfeng Tao; Huawen Liang; Wei Yuan 006; Teng Tian; Shuang Xue; Xi Jin 002 (HPEC, 2021)

An SSD-Based Accelerator for Singular Value Decomposition Recommendation Algorithm on Edge. - Wei Wu; Letian Zhao; Qizhe Wu; Xiaotian Wang; Teng Tian; Xi Jin 002 (HPEC, 2022)

HuGraph: Acceleration of GCN Training on Heterogeneous FPGA Clusters with Quantization. - Letian Zhao; Qizhe Wu; Xiaotian Wang; Teng Tian; Wei Wu; Xi Jin 002 (HPEC, 2022)

FP-GNN: Adaptive FPGA accelerator for Graph Neural Networks. - Teng Tian; Letian Zhao; Xiaotian Wang; Qizhe Wu; Wei Yuan 006; Xi Jin 002 (Future Gener. Comput. Syst., 2022)

QEGCN: An FPGA-based accelerator for quantized GCNs with edge-level parallelism. - Wei Yuan 006; Teng Tian; Qizhe Wu; Xi Jin 002 (J. Syst. Archit., 2022)

Scheduling Memory Access Optimization for HBM Based on CLOS. - Shuang Xue; Huawei Liang; Qizhe Wu; Xi Jin 002 (ICACT, 2023)

FTW-GAT: An FPGA-Based Accelerator for Graph Attention Networks With Ternary Weights. - Zerong He; Teng Tian; Qizhe Wu; Xi Jin 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A FPGA-HBM-Based Hardware Streaming Accelerator for GNN Sampling. - Yuchen Gui; Qizhe Wu; Wei Yuan 006; Huawen Liang; Xiaotian Wang; Xi Jin 002 (ASAP, 2024)

RingTK: A Ring, Parallel and High Performance Top-K Sorter on FPGA. - Huawen Liang; Qizhe Wu; Wei Yuan 006; Teng Tian; Xi Jin 002 (FCCM, 2024)

Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. - Qizhe Wu; Letian Zhao; Yuchen Gui; Huawen Liang; Xiaotian Wang; Xi Jin 002 (FPGA, 2024)

HBM-Based Hardware Accelerator for GNN Sampling and Aggregation. - Yuchen Gui; Qizhe Wu; Wei Yuan 006; Huawen Liang; Xiaotian Wang; Xi Jin 002 (HPEC, 2024)

EN-T: Optimizing Tensor Computing Engines Performance via Encoder-Based Methodology. - Qizhe Wu; Yuchen Gui; Zhichen Zeng 002; Xiaotian Wang; Huawen Liang; Xi Jin 002 (ICCD, 2024)

EN-TensorCore: Advancing TensorCores Performance through Encoder-Based Methodology. - Qizhe Wu; Yuchen Gui; Zhichen Zeng 002; Xiaotian Wang; Huawen Liang; Xi Jin 002 (CoRR, 2024)

Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks. - Qizhe Wu; Letian Zhao; Yuchen Gui; Huawen Liang; Xiaotian Wang (CoRR, 2024)

Exploring the Performance Improvement of Tensor Processing Engines through Transformation in the Bit-weight Dimension of MACs. - Qizhe Wu; Huawen Liang; Yuchen Gui; Zhichen Zeng 002; Zerong He; Linfeng Tao; Xiaotian Wang; Letian Zhao; Zhaoxi Zeng; Wei Yuan 006; Wei Wu; Xi Jin 002 (HPCA, 2025)