A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. - Zhengxiong Hou; Yipeng Wang 003; Quan Pan 002; C. Patrick Yue (ASICON, 2013)

A 65-nm CMOS P-well/Deep N-well avalanche photodetector for integrated 850-nm optical. - Quan Pan 002; Zhengxiong Hou; Yipeng Wang 003; C. Patrick Yue (ASICON, 2013)

A 41-mW 30-Gb/s CMOS optical receiver with digitally-tunable cascaded equalization. - Quan Pan 002; Yipeng Wang 003; Zhengxiong Hou; Li Sun; Liang Wu; Wing-Hung Ki; Patrick Chiang 001; C. Patrick Yue (ESSCIRC, 2014)

A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. - Quan Pan 002; Zhengxiong Hou; Yipeng Wang 003; Yan Lu 002; Wing-Hung Ki; Keh-Chung Wang; C. Patrick Yue (VLSIC, 2014)

A 26-28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS. - Li Sun; Quan Pan 002; Keh-Chung Wang; C. Patrick Yue (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 60GHz 4Gb/s fully integrated NRZ-to-QPSK modulator SoC for backhaul links in fiber-wireless networks. - Yipeng Wang 003; Duona Luo; Quan Pan 002; Liwen Jing; Zhixin Li; C. Patrick Yue (ESSCIRC, 2015)

A Fully-Integrated Low-Dropout Regulator With Full-Spectrum Power Supply Rejection. - Yan Lu 002; Yipeng Wang 003; Quan Pan 002; Wing-Hung Ki; C. Patrick Yue (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A low-power PAM4 receiver using 1/4-rate sampling decoder with adaptive variable-gain rectification. - Guang Zhu; Quan Pan 002; John Zhuang; Charlie Zhi; C. Patrick Yue (A-SSCC, 2017)

A 60-GHz 4-Gb/s Fully Integrated NRZ-to-QPSK Fiber-Wireless Modulator. - Yipeng Wang 003; Duona Luo; Quan Pan 002; Liwen Jing; Zhixin Li; C. Patrick Yue (IEEE Trans. Circuits Syst. I Regul. Pap., 2017)

Wideband Variable-Gain Amplifiers Based on a Pseudo-Current-Steering Gain-Tuning Technique. - Lingshan Kong; Yong Chen 005; Haohong Yu; Quan Pan 002; Chirn Chye Boon; Pui-In Mak; Rui Paulo Martins (APCCAS, 2019)

A 50Gb/s PAM-4 Retimer-CDR + VCSEL Driver with Asymmetric Pulsed Pre-Emphasis Integrated into a Single CMOS Die. - Shang Hu; Tingyu Yao; Bozhi Yin; Chunyu Song; Lei Zhao; Juncheng Wang; Lei Wang 187; Rui Bai 001; Xin Wang 130; Tao Xia; Yi Peng; Binbin Yao; et al. (OFC, 2019)

A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. - Juncheng Wang; Quan Pan 002; Yajie Qin; Xuefeng Chen 004; Shang Hu; Rui Bai 001; Xin Wang 130; Yaxin Cai; Tao Xia; Yuanxi Zhang; Jianxu Ma; Nan Qi; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 224-Gb/s PAM4 High-Linearity, Energy-Efficiency Differential to Single-Ended Driver in 130-nm SiGe BiCMOS. - Jiahan Fu; Pingyi Cai; Xiongshi Luo; Xuewei You; Liping Zhong; Wenbo Xiao; Fujiang Lin; Yao Li; Quan Pan 002 (ICTA, 2020)

Fully-Differential 100-Gb/s PAM4 Cross-Coupled Regulated Transimpedance Amplifier. - Dongfan Xu; Zhang Qiu; Xiongshi Luo; Xuewei You; Wenbo Xiao; Siqiang Zhu; Minzhe Tang; Zhenghao Li; Quan Pan 002 (ICTA, 2020)

A 112-Gb/s PAM-4 Linear Optical Receiver in 130-nm SiGe BiCMOS. - Dan Li 011; Shengwei Gao; Yongjun Shi; Xiaoyan Gui; Nan Qi; Zhiyong Li 014; Quan Pan 002; Patrick Chiang 001; Li Geng (ISCAS, 2020)

PAM-X™: A 25Gb/s-PAM4 Optical Transceiver Chipset for 5G Optical Front-Haul. - Xin Wang 130; Yi Peng; Yuanxi Zhang; Tao Xia; Yifan Wu 009; Juncheng Wang; Lei Wang 187; Liujia Song; Lei Zhao; Shenglong Zhuo; Quan Pan 002; Xuefeng Chen 004; et al. (OFC, 2020)

A 15-Gb/s 0.0037-mm² 0.019-pJ/Bit Full-Rate Programmable Multi-Pattern Pseudo-Random Binary Sequence Generator. - Junfeng Hu; Zhao Zhang 004; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A -40 °C to 120 °C, 169 ppm/°C Nano-Ampere CMOS Current Reference. - Qiwei Huang; Chenchang Zhan; Lidan Wang 001; Zhiqun Li; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 42-dB Ω 25-Gb/s CMOS Transimpedance Amplifier With Multiple-Peaking Scheme for Optical Communications. - Quan Pan 002; Yipeng Wang 003; C. Patrick Yue (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Low-Power PAM4 Receiver With an Adaptive Variable-Gain Rectifier-Based Decoder. - Quan Pan 002; Li Wang 083; Xiongshi Luo; C. Patrick Yue (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 720-mVpp 224-Gb/s PAM4 Optical Receiver with Multiple Peaking Techniques in 130-nm SiGe BiCMOS. - Qi Zhang; Xiongshi Luo; Zhenghao Li; Dongfan Xu; Siqiang Zhu; Leiming Wang; Zhenjiang Mao; Xiaoyan Gui; Dan Li 011; Hongyu Yu; Quan Pan 002 (APCCAS, 2021)

Design and Co-Simulation of QPSK and NRZ/PAM-4/PAM-8 VCSEL-Based Optical Links Utilizing an Integrated System Evaluation Engine. - Fuzhan Chen; Chongyun Zhang; Tianxin Min; Bo Xu; Quan Pan 002; C. Patrick Yue (ASICON, 2021)

A 100GBaud Optical Receiver Front-End in 90nm SiGe BiCMOS. - Chuanhao Yu; Zhenyu Yin; Chenfan Cao; Shiti Huang; Quan Pan 002; Xiaoyan Gui; Li Geng; Dan Li 011 (ICTA, 2021)

An Area-Efficient Low Quiescent Current Output Capacitor-Less LDO with Fast Transient Response. - Hongchang Qiao; Chenchang Zhan; Quan Pan 002; Yutian Chen; Ning Zhang (ISCAS, 2021)

8.5 A Scalable Adaptive ADC/DSP-Based 1.25-to-56Gbps/112Gbps High-Speed Transceiver Architecture Using Decision-Directed MMSE CDR in 16nm and 7nm. - Danfeng Xu; Yu Kou; Paul Lai; Zichuan Cheng; Tze Yin Cheung; Larry Moser; Yang Zhang; Xiaolong Liu; Man Pio Lam; Haikun Jia; Quan Pan 002; Wing Hong Szeto; et al. (ISSCC, 2021)

A 57-100 ​GHz 0.13 ​μm SiGe power amplifier with high output power and efficiency. - Hamed Mosalam; Quan Pan 002 (Microelectron. J., 2021)

A 56-Gb/s PAM4 Receiver Analog Front-End With Fixed Peaking Frequency and Bandwidth in 40-nm CMOS. - Zhenghao Li; Minzhe Tang; Taiyang Fan; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 19-48.3-GHz 6th-Order Transformer-Based Injection-Locked Frequency Divider With 87.1% Locking Range in 40-nm CMOS. - Junhua Zhu; Qiyao Jiang; Hamed Mosalam; Chenchang Zhan; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove. - Juncheng Wang; Xuefeng Chen 004; Rui Bai 001; Patrick Yin Chiang; Quan Pan 002 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

A 4-Vppd160-Gb/s PAM-4 Optical Modulator Driver with All-Pass Filter-Based Dynamic Bias and 2- Tap FFE in 130-nm BiCMOS. - Shuo Feng; Fuzhan Chen; Zhenghao Li; Wentao Zhou; Dongfan Xu; Chun-Zhang Chen; Xuhui Liu; Hanming Wu; Quan Pan 002 (APCCAS, 2022)

A 160-Gb/s 0.37-pJ/bit PAM4 Optical Receiver in 28-nm CMOS. - Leiming Wang; Xiongshi Luo; Dongfan Xu; Zhang Qiu; Yiyang Yan; Quan Pan 002 (APCCAS, 2022)

A 112-Gb/s Single-Ended PAM-4 Transceiver Front-End for Reach Extension in Long-Reach Link. - Xiongshi Luo; Xuewei You; Jiahan Fu; Zhenghao Li; Liping Zhong; Taiyang Fan; Zhang Qiu; Wenbo Xiao; Yong Chen 005; Quan Pan 002 (ESSCIRC, 2022)

A 2×50Gb/s Single-Ended MIMO PAM-4 Crosstalk Cancellation and Signal Reutilization Receiver in 28 nm CMOS. - Liping Zhong; Hongzhi Wu; Weitao Wu; Wenbo Xiao; Xiongshi Luo; Dongfan Xu; Xuxu Cheng; Zhenghao Li; Taiyang Fan; Quan Pan 002 (ESSCIRC, 2022)

A 200-Gb/s PAM-4 Feedforward Linear Equalizer with Multiple-Peaking and Fixed Maximum Peaking Frequencies in 130nm SiGe BiCMOS. - Zhengzhe Jia; Taiyang Fan; Dongfan Xu; Dongshen Zhan; Linxuan Hu; Zhengyang Zhang; Yanchao Wang; Chun-Zhang Chen; Xuhui Liu; Hanming Wu; Quan Pan 002 (ICTA, 2022)

Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS. - Qiyao Jiang; Quan Pan 002 (IEEE J. Solid State Circuits, 2022)

A 6.15-10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With "Phase Reset" Scheme. - Wenbo Xiao; Qiwei Huang; Hamed Mosalam; Chenchang Zhan; Zhiqun Li; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A 54-68 GHz Power Amplifier With Improved Linearity and Efficiency in 40 nm CMOS. - Hamed Mosalam; Wenbo Xiao; Xiaoyan Gui; Dan Li 011; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 2 x 24Gb/s Single-Ended Transceiver with Channel-Independent Encoder-Based Crosstalk Cancellation in 28nm CMOS. - Hongzhi Wu; Weitao Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Zhenghao Li; Dongfan Xu; Quan Pan 002 (A-SSCC, 2023)

A 2.05-pJ/b 56-Gb/s PAM-4 VCSEL Transmitter with Piecewise Nonlinearity Compensation and Asymmetric Equalization in 40-nm CMOS. - Fuzhan Chen; Chongyun Zhang; Li Wang 083; Quan Pan 002; C. Patrick Yue (ESSCIRC, 2023)

A Power-Efficient $ boldsymbol{4}- mathbf{V}_{ mathbf{ppd}}$ 128-Gb/s PAM-4 Optical Modulator Driver with Merged BV Doubler Topology in 130-nm BiCMOS. - Shuo Feng; Fuzhan Chen; Quan Pan 002 (ICTA, 2023)

A 28-Gb/s PAM-4 Fully-Integrated Optical Receiver with High-Speed Silicon Photodetector in 28-nm CMOS. - Dongshen Zhan; Liping Zhong; Wentao Zhou; Zhenyu Yao; Xiongshi Luo; Yangyi Zhang; Hemiao Wang; De Zhou; Quan Pan 002 (ICTA, 2023)

A Fully-Integrated LDO with Two-Stage Cross-Coupled Error Amplifier for High-Speed Communications in 28-nm CMOS. - Dongfan Xu; Yangyi Zhang; Zhenghao Li; Xiongshi Luo; Pingyi Cai; Hongzhi Wu; Liping Zhong; Weitao Wu; Liru Zhu; Quan Pan 002 (ISCAS, 2023)

A CMOS slew-rate controlled output driver with low process, voltage and temperature variations using a dual-path signal-superposition technique. - Xiaoyan Gui; Renjie Tang; Kai Li; Kanan Wang; Dan Li 011; Quan Pan 002; Li Geng (IET Circuits Devices Syst., 2023)

A 0.96-0.9-V Fully Integrated FVF LDO With Two-Stage Cross-Coupled Error Amplifier. - Dongfan Xu; Yangyi Zhang; Xiongshi Luo; Zhenghao Li; Quan Pan 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 56-Gbaud 7.3-Vppd Linear Modulator Transmitter with AMUX-Based Reconfigurable FFE and Dynamic Triple-Stacked Driver in 130-nm SiGe BiCMOS. - Fuzhan Chen; C. Patrick Yue; Quan Pan 002 (CICC, 2024)

A 128Gb/s PAM-4 Transmitter with Edge-Boosting Pulse Generator and Pre-Emphasis Asymmetric Fractional-Spaced FFE in 28nm CMOS. - Hongzhi Wu; Weitao Wu; Liping Zhong; Xuxu Cheng; Yangyi Zhang; Xiongshi Luo; Dongfan Xu; Xindan Yu; Quan Pan 002 (CICC, 2024)

A 6.0-to-6.9GHz 99fsrms-Jitter Type-II Sampling PLL with Automatic Frequency and Phase Calibration Method Achieving 0.62μs Locking Time in 28nm CMOS. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Pui-In Mak; Rui Paulo Martins; Quan Pan 002 (CICC, 2024)

A High Linearity Driver with a Wide Common-Mode Voltage Range in 130-nm BiCMOS. - Jiayao Li; Jian Yang; Taiyang Fan; Kun Zhang; Junhua Zhu; Quan Pan 002 (ICTA, 2024)

7.5 A 224Gb/s/wire Single-Ended PAM-4 Transceiver Front-End with 29dB Equalization for 800GbE/1.6TbE. - Xiongshi Luo; Xuewei You; Zhenghao Li; Hamed Mosalam; Dongfan Xu; Taiyang Fan; Hongchang Qiao; Wentao Zhou; Hongzhi Wu; Liping Zhong; Patrick Yin Chiang; Quan Pan 002 (ISSCC, 2024)

13.5 A 64Gb/s/pin PAM4 Single-Ended Transmitter with a Merged Pre-Emphasis Capacitive-Peaking Crosstalk-Cancellation Scheme for Memory Interfaces in 28nm CMOS. - Weitao Wu; Hongzhi Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Dongfan Xu; Catherine Wang; Zhenghao Li; Quan Pan 002 (ISSCC, 2024)

7.6 A 112Gb/s/pin Single-Ended Crosstalk-Cancellation Transceiver with 31dB Loss Compensation in 28nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Quan Pan 002 (ISSCC, 2024)

A 2×56Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS. - Xuxu Cheng; Hongzhi Wu; Liping Zhong; Weitao Wu; Quan Pan 002 (VLSI Technology and Circuits, 2024)

A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS. - Chongyun Zhang; Li Wang 083; Zilu Liu; Fuzhan Chen; Quan Pan 002; Xianbo Li; C. Patrick Yue (VLSI Technology and Circuits, 2024)

A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. - Liping Zhong; Yangyi Zhang; Xiongshi Luo; Hongzhi Wu; Xuxu Cheng; Weitao Wu; Zhenghao Li; Quan Pan 002 (VLSI Technology and Circuits, 2024)

A 2×56 Gb/s 0.78-pJ/b PAM-4 Crosstalk Cancellation Receiver With Active Crosstalk Extraction Technique in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Weitao Wu; Catherine Wang; Wenbo Xiao; Xiongshi Luo; Yangyi Zhang; Dongfan Xu; Wei Wang 433; Taiyang Fan; Zhenghao Li; Xuxu Cheng; et al. (IEEE J. Solid State Circuits, 2024)

Signal Integrity Augmentation Techniques for the Design of 64-GBaud Coherent Transimpedance Amplifier in 90-nm SiGe BiCMOS. - Shuaizhe Ma; Nianquan Ran; Xi Liu; Yifei Xia; Songqin Xu; Wei Huang; Chen Tan; Jing Li; Zhenyu Yin; Shaoheng Lin; Jianhua Pan; Zhe Chen; et al. (IEEE Trans. Circuits Syst. I Regul. Pap., 2024)

A 0.3-to-10.1 GHz 33.8fSRMS-Jitter Hybrid Injection-Locked Eight-Phase Clock Generator with Adaptive Mismatch Cancellation Technique for High-Speed Links in 28nm CMOS. - Hongzhi Wu; Xuxu Cheng; Liping Zhong; Yangyi Zhang; Weitao Wu; Xiongshi Luo; Quan Pan 002 (CICC, 2025)

A 100Gbaud 4Vppd Distributed Linear Driver with Cross-Folded Transmission Lines and Cross-Coupled Gm Cells for Built-in 5-Tap FFE in 0.13µm SiGe BiCMOS. - Fuzhan Chen; C. Patrick Yue; Quan Pan 002 (ISSCC, 2025)

36.6 A 112Gb/s 0.61pJ/b PAM-4 Linear TIA Supporting Extended PD-TIA Reach in 28nm CMOS. - Yangyi Zhang; Zhenyu Yao; Wentao Zhou; Xiongshi Luo; Zhenghao Li; Dongshen Zhan; Quan Pan 002 (ISSCC, 2025)

A 64 Gb/s/pin Single-Ended PAM-4 Transmitter With a Merged Preemphasis Capacitive-Peaking Crosstalk Cancellation Scheme for Memory Interfaces in 28-nm CMOS. - Weitao Wu; Hongzhi Wu; Liping Zhong; Xuxu Cheng; Xiongshi Luo; Dongfan Xu; Catherine Wang; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

A 2 × 112 Gb/s/pin Single-Ended Crosstalk Cancellation Transceiver With 31-dB Loss Compensation in 28-nm CMOS. - Liping Zhong; Hongzhi Wu; Yangyi Zhang; Xuxu Cheng; Weitao Wu; Catherine Wang; Xiongshi Luo; Taiyang Fan; Dongfan Xu; Zhenghao Li; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

A 2 × 24 Gb/s Single-Ended Transceiver With Channel-Independent Encoder-Based Crosstalk Cancellation in 28-nm CMOS. - Hongzhi Wu; Liping Zhong; Weitao Wu; Catherine Wang; Xuxu Cheng; Xiongshi Luo; Yangyi Zhang; Dongfan Xu; Quan Pan 002 (IEEE J. Solid State Circuits, 2025)

Design and Analysis of a Type-II Sampling PLL With Automatic Frequency and Phase Calibrations Achieving 0.62-μs Locking Time. - Jian Yang; Tailong Xu; Xi Meng; Zhenghao Li; Jun Yin 001; Rui Paulo Martins; Pui-In Mak; Quan Pan 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)