Virtual Platform to Analyze the Security of a System on Chip at Microarchitectural Level. - Quentin Forcioli; Jean-Luc Danger; Clémentine Maurice; Lilian Bossuet; Florent Bruguier; Maria Mushtaq; David Novo; Loïc France; Pascal Benoit; Sylvain Guilley; Thomas Perianin (EuroS&P Workshops, 2021)

A gem5 based Platform for Micro-Architectural Security Analysis. - Quentin Forcioli; Jean-Luc Danger; Sumanta Chaudhuri (HASP@MICRO, 2023)

TEE-Time: A Dynamic Cache Timing Analysis Tool for Trusted Execution Environments. - Quentin Forcioli; Sumanta Chaudhuri; Jean-Luc Danger (ISQED, 2024)

Modeling of micro-architecture for security with gem5. (Modélisation des micro-architectures pour la sécurité avec la plate-forme Gem5). - Quentin Forcioli (2024)

Defeating AutoLock: From Simulation to Real-World Cache-Timing Exploits against TrustZone. - Quentin Forcioli; Sumanta Chaudhuri; Jean-Luc Danger (IACR Cryptol. ePrint Arch., 2025)