Lightweight Transactional Memory systems for NoCs based architectures: Design, implementation and comparison of two policies. - Quentin L. Meunier; Frédéric Pétrot (J. Parallel Distributed Comput., 2010)

Hardware/software support for adaptive work-stealing in on-chip multiprocessor. - Quentin L. Meunier; Frédéric Pétrot; Jean-Louis Roch (J. Syst. Archit., 2010)

Étude de deux solutions pour le support matériel de la programmation parallèle dans les multiprocesseurs intégrés : vol de travail et mémoires transactionnelles. (Study of two Solutions for Hardware Support of Parallel Programming in Integrated Multiprocessors: Work-Stealing and Transactional Memory). - Quentin L. Meunier (2010)

Fixed-point accuracy evaluation in the context of conditional structures. - Jean-Charles Naud; Quentin L. Meunier; Daniel Ménard; Olivier Sentieys (EUSIPCO, 2011)

Systèmes de mémoire transactionnelle pour les architectures à base de NoC Conception, implémentation et comparaison de deux politiques. - Quentin L. Meunier; Frédéric Pétrot (Tech. Sci. Informatiques, 2011)

RWT: Suppressing Write-Through Cost When Coherence is Not Needed. - Hao Liu; Clement Devigne; Lucas Garcia; Quentin L. Meunier; Franck Wajsbürt; Alain Greiner (ISVLSI, 2015)

GECOS : Mécanisme de synchronisation passant à l'échelle à plusieurs lecteurs et un écrivain pour structures chaînées. - Mohamed Lamine Karaoui; Quentin L. Meunier; Franck Wajsbürt; Alain Greiner (Tech. Sci. Informatiques, 2015)

Exploiting Large Memory Using 32-Bit Energy-Efficient Manycore Architectures. - Mohamed Lamine Karaoui; Pierre-Yves Peneau; Quentin L. Meunier; Franck Wajsbürt; Alain Greiner (MCSoC, 2016)

Symbolic Approach for Side-Channel Resistance Analysis of Masked Assembly Codes. - Inès Ben El Ouahma; Quentin L. Meunier; Karine Heydemann; Emmanuelle Encrenaz (PROOFS, 2017)

Decoupling Translation Lookaside Buffer Coherence from Cache Coherence. - Hao Liu; Quentin L. Meunier; Alain Greiner (ISVLSI, 2017)

Executing secured virtual machines within a manycore architecture. - Clement Devigne; Jean-Baptiste Bréjon; Quentin L. Meunier; Franck Wajsbürt (Microprocess. Microsystems, 2017)

A new Direct Connected Component Labeling and Analysis Algorithms for GPUs. - Arthur M. Hennequin; Lionel Lacassagne; Laurent Cabaret; Quentin L. Meunier (DASIP, 2018)

Energy and Execution Time Comparison of Optical Flow Algorithms on SIMD and GPU Architectures. - Andrea Petreto; Arthur M. Hennequin; Thomas Koehler; Thomas Romera; Yohan Fargeix; Boris Gaillard; Manuel Bouyer; Quentin L. Meunier; Lionel Lacassagne (DASIP, 2018)

A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches. - Eric Guthmuller; César Fuguet Tortolero; Pascal Vivet; Christian Bernard; Ivan Miro Panades; Jean Durupt; E. Beignc; Didier Lattard; Séverine Cheramy; Alain Greiner; Quentin L. Meunier; Pirouz Bazargan-Sabet (ESSCIRC, 2018)

Modeling a Cache Coherence Protocol with the Guarded Action Language. - Quentin L. Meunier; Yann Thierry-Mieg; Emmanuelle Encrenaz (MARS/VPT@ETAPS, 2018)

A New Real-Time Embedded Video Denoising Algorithm. - Andrea Petreto; Thomas Romera; Florian Lemaitre; Ian Masliah; Boris Gaillard; Manuel Bouyer; Quentin L. Meunier; Lionel Lacassagne (DASIP, 2019)

Side-channel robustness analysis of masked assembly codes using a symbolic approach. - Inès Ben El Ouahma; Quentin L. Meunier; Karine Heydemann; Emmanuelle Encrenaz (J. Cryptogr. Eng., 2019)

2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm2 Inter-Chiplet Interconnects and 156mW/mm2@ 82%-Peak-Efficiency DC-DC Converters. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; Guillaume Moritz; Ivan Miro-Panades; César Fuguet Tortolero; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (ISSCC, 2020)

Maskara: Compilation of a Masking Countermeasure With Optimized Polynomial Interpolation. - Nicolas Belleville; Damien Couroussé; Karine Heydemann; Quentin L. Meunier; Inès Ben El Ouahma (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Implementations Impact on Iterative Image Processing for Embedded GPU. - Thomas Romera; Andrea Petreto; Florian Lemaitre; Manuel Bouyer; Quentin L. Meunier; Lionel Lacassagne (EUSIPCO, 2021)

LeakageVerif: Scalable and Efficient Leakage Verification in Symbolic Expressions. - Quentin L. Meunier; Etienne Pons; Karine Heydemann (IACR Cryptol. ePrint Arch., 2021)

IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management. - Pascal Vivet; Eric Guthmuller; Yvain Thonnart; Gaël Pillonnet; César Fuguet Tortolero; Ivan Miro-Panades; Guillaume Moritz; Jean Durupt; Christian Bernard; Didier Varreau; Julian J. H. Pontes; Sébastien Thuries; et al. (IEEE J. Solid State Circuits, 2021)

Armistice: Micro-Architectural Leakage Modelling for Masked Software Formal Verification. - Arnaud de Grandmaison; Karine Heydemann; Quentin L. Meunier (IACR Cryptol. ePrint Arch., 2022)

ARMISTICE: Microarchitectural Leakage Modeling for Masked Software Formal Verification. - Arnaud de Grandmaison; Karine Heydemann; Quentin L. Meunier (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

VerifMSI: Practical Verification of Hardware and Software Masking Schemes Implementations. - Quentin L. Meunier; Abdul Rahman Taleb (IACR Cryptol. ePrint Arch., 2023)

Optical flow algorithms optimized for speed, energy and accuracy on embedded GPUs. - Thomas Romera; Andrea Petreto; Florian Lemaitre; Manuel Bouyer; Quentin L. Meunier; Lionel Lacassagne; Daniel Etiemble (J. Real Time Image Process., 2023)

LeakageVerif: Efficient and Scalable Formal Verification of Leakage in Symbolic Expressions. - Quentin L. Meunier; Etienne Pons; Karine Heydemann (IEEE Trans. Software Eng., 2023)

Blind-Folded: Simple Power Analysis Attacks using Data with a Single Trace and no Training. - Xunyue Hu; Quentin L. Meunier; Emmanuelle Encrenaz (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)