Intermediate Address Space: virtual memory optimization of heterogeneous architectures for cache-resident workloads. - Qunyou Liu; Darong Huang; Luis Costero; Marina Zapater; David Atienza (ACM Trans. Archit. Code Optim., 2024)

Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel Accelerators. - Qunyou Liu; Marina Zapater; David Atienza (CoRR, 2025)

MatrixFlow: System-Accelerator co-design for high-performance transformer applications. - Qunyou Liu; Marina Zapater; David Atienza (CoRR, 2025)