Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations. - Qunzeng Liu; Sachin S. Sapatnekar (DAC, 2007)

Synthesizing a representative critical path for post-silicon delay prediction. - Qunzeng Liu; Sachin S. Sapatnekar (ISPD, 2009)

A Framework for Scalable Postsilicon Statistical Delay Prediction Under Process Variations. - Qunzeng Liu; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

Capturing Post-Silicon Variations Using a Representative Critical Path. - Qunzeng Liu; Sachin S. Sapatnekar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Process and Reliability Sensors for Nanoscale CMOS. - John Keane 001; Chris H. Kim; Qunzeng Liu; Sachin S. Sapatnekar (IEEE Des. Test Comput., 2012)