Strain and layout management in dual channel (sSOI substrate, SiGe channel) planar FDSOI MOSFETs. - François Andrieu; Mikaël Cassé; E. Baylac; P. Perreau; O. Nier; Denis Rideau; R. Berthelon; Franck Pourchon; A. Pofelski; Barbara De Salvo; C. Gallon; Vincent Mazzocchi; et al. (ESSDERC, 2014)

Performance and layout effects of SiGe channel in 14nm UTBB FDSOI: SiGe-first vs. SiGe-last integration. - R. Berthelon; François Andrieu; P. Perreau; E. Baylac; A. Pofelski; Emmanuel Josse; Didier Dutartre; A. Claverie; Michel Haond (ESSDERC, 2016)

Improving Ge-rich GST ePCM reliability through BEOL engineering. - Andrea Redaelli; Anna Gandolfo; Giulia Samanni; Enrico Gomiero; Elisa Petroni; Luca Scotti; Andrea Lippiello; Paolo Mattavelli; J. Jasse; D. Codegoni; A. Serafini; Rossella Ranica; et al. (ESSDERC, 2021)

Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration. - R. Berthelon; Olivier Weber; F. Ibars; B. Revel; C. Borowiak; J. C. Grenier; B. Dumont; S. Desmoulins; P. O. Sassoulas; P. Ferreira; S. Chouteau; S. Niel; et al. (VLSI Technology and Circuits, 2024)