Substrate Engineering to Improve Soft-Error-Rate Immunity for SRAM Technologies. - Helmut Puchner; Y.-C. Liu; W. Kong; F. Duan; R. Castagnetti (Microelectron. Reliab., 2001)

Design and Use of Memory-Specific Test Structures to Ensure SRAM Yield and Manufacturability. - F. Duan; R. Castagnetti; R. Venkatraman; O. Kobozeva; S. Ramesh 004 (ISQED, 2003)

The Statistics of Device Variations and its Impact on SRAM Bitcell Performance, Leakage and Stability. - R. Venkatraman; R. Castagnetti; S. Ramesh 004 (ISQED, 2006)

Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. - R. Venkatraman; R. Castagnetti; Andres Teene; Benjamin Mbouombouo; S. Ramesh 004 (ISQED, 2009)