Efficient Testing of Tree Circuits. - Ronald D. Blanton; John P. Hayes (FTCS, 1993)

Design and testing of regular circuits. - R. D. (Shawn) Blanton (1995)

Synthesis of Self-Testing Finite State Machines from High-Level Specifications. - Vishwani D. Agrawal; Ronald D. Blanton; Maurizio Damiani (ITC, 1996)

Design of a fast, easily testable ALU. - R. D. (Shawn) Blanton; John P. Hayes (VTS, 1996)

Testability of Convergent Tree Circuits. - Ronald D. Blanton; John P. Hayes (IEEE Trans. Computers, 1996)

The input pattern fault model and its application. - Ronald D. Blanton; John P. Hayes (ED&TC, 1997)

Development of a MEMS Testing Methodology. - Abhijeet Kolpekwar; Ronald D. Blanton (ITC, 1997)

To DFT or Not to DFT? - Sichao Wei; Pranab K. Nag; Ronald D. Blanton; Anne E. Gattiker; Wojciech Maly (ITC, 1997)

Testability Properties of Divergent Trees. - R. D. (Shawn) Blanton; John P. Hayes (J. Electron. Test., 1997)

Using regression analysis for GA-based ATPG parameter optimization. - William E. Dougherty; R. D. (Shawn) Blanton (ICCD, 1998)

Failure modes for stiction in surface-micromachined MEMS. - Abhijeet Kolpekwar; Ronald D. Blanton; David Woodilla (ITC, 1998)

MEMS fault model generation using CARAMEL. - Abhijeet Kolpekwar; Chris S. Kellen; Ronald D. Blanton (ITC, 1998)

Testing MEMS. - Jean-Michel Karam; Marcelo Lubaszewski; R. D. Shawn Blanton; Andrew Richardson 001 (VTS, 1998)

Particulate failures for surface-micromachined MEMS. - Tao Jiang 028; Ronald D. Blanton (ITC, 1999)

IDDQ-Testability of Tree Circuits. - R. D. (Shawn) Blanton (VLSI Design, 1999)

Superscalar Processor Validation at the Microarchitecture Level. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (VLSI Design, 1999)

Guest Editors' Introduction. - Bernard Courtois; R. D. (Shawn) Blanton (IEEE Des. Test Comput., 1999)

Hierarchical Design and Test of Integrated Microsystems. - Tamal Mukherjee; Gary K. Fedder; R. D. (Shawn) Blanton (IEEE Des. Test Comput., 1999)

An integrated functional performance simulator. - Candice Bechem; Jonathan Combs; Noppanunt Utamaphethai; Bryan Black; R. D. (Shawn) Blanton; John Paul Shen (IEEE Micro, 1999)

Universal fault simulation using fault tuples. - Kumar N. Dwarakanath; Ronald D. Blanton (DAC, 2000)

Analysis of failure sources in surface-micromachined MEMS. - Nilmoni Deb; Ronald D. Blanton (ITC, 2000)

Universal test generation using fault tuples. - Rao Desineni; Kumar N. Dwarakanath; Ronald D. Blanton (ITC, 2000)

Identification of crosstalk switch failures in domino CMOS circuits. - Rahul Kundu; Ronald D. Blanton (ITC, 2000)

Effectiveness of Microarchitecture Test Program Generation. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (IEEE Des. Test Comput., 2000)

A Buffer-Oriented Methodology for Microarchitecture Validation. - Noppanunt Utamaphethai; R. D. (Shawn) Blanton; John Paul Shen (J. Electron. Test., 2000)

On the design of fast, easily testable ALU's. - Ronald D. Blanton; John P. Hayes (IEEE Trans. Very Large Scale Integr. Syst., 2000)

False Coupling Interactions in Static Timing Analysis. - Ravishankar Arunachalam; Ronald D. Blanton; Lawrence T. Pileggi (DAC, 2001)

Relating buffer-oriented microarchitecture validation to high-level pipeline functionality. - Noppanunt Utamaphethai; Ronald D. Blanton; John Paul Shen (HLDVT, 2001)

Designing and Implementing Efficient BISR Techniques for Embedded RAMs. - Michael Nicolaidis; Slimane Boutobza; Nadir Achouri; R. D. Shawn Blanton; Julie Segal; David Y. Lepejian; Ben Chu; Tony Singh; Harvey Berman (LATW, 2001)

Testing of Dynamic Logic Circuits Based on Charge Sharing. - Keerthi Heragu; Manish Sharma; Rahul Kundu; R. D. (Shawn) Blanton (VTS, 2001)

Fault Tuples in Diagnosis of Deep-Submicron Circuits. - Ronald D. Blanton; John T. Chen; Rao Desineni; Kumar N. Dwarakanath; Wojciech Maly; Thomas J. Vogels (ITC, 2002)

Built-In Self Test of CMOS-MEMS Accelerometers. - Nilmoni Deb; R. D. (Shawn) Blanton (ITC, 2002)

Exploiting Dominance and Equivalence using Fault Tuples. - Kumar N. Dwarakanath; R. D. (Shawn) Blanton (VTS, 2002)

Timed Test Generation Crosstalk Switch Failures in Domino CMOS Circuits. - Rahul Kundu; R. D. (Shawn) Blanton (VTS, 2002)

SoCs with MEMS? Can We Include MEMS in the SoCs Design and Test Flow? - Salvador Mir; H. Bederr; R. D. (Shawn) Blanton; Hans G. Kerkhoff; H. J. Klim (VTS, 2002)

Modeling the Economics of Testing: A DFT Perspective. - Pranab K. Nag; Anne E. Gattiker; Sichao Wei; Ronald D. Blanton; Wojciech Maly (IEEE Des. Test Comput., 2002)

Test vector generation for charge sharing failures in dynamic logic. - Keerthi Heragu; Manish Sharma; Rahul Kundu; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

Accurate Coupling-centric Timing Analysis Incorporating Temporal and Functional Isolation. - Ravishankar Arunachalam; Ronald DeShawn Blanton; Lawrence T. Pileggi (VLSI Design, 2002)

ATPG for Noise-Induced Switch Failures in Domino Logic. - Rahul Kundu; R. D. (Shawn) Blanton (ICCAD, 2003)

Analyzing the Effectiveness of Multiple-Detect Test Sets. - R. D. (Shawn) Blanton; Kumar N. Dwarakanath; Anirudh B. Shah (ITC, 2003)

Path Delay Test Generation for Domino Logic Circuits in the Presence of Crosstalk. - Rahul Kundu; R. D. (Shawn) Blanton (ITC, 2003)

Deformations of IC Structure in Test and Yield Learning. - Wojciech Maly; Anne E. Gattiker; Thomas Zanon; Thomas J. Vogels; R. D. (Shawn) Blanton; Thomas M. Storey (ITC, 2003)

Progressive Bridge Identification. - Thomas J. Vogels; Wojciech Maly; R. D. (Shawn) Blanton (ITC, 2003)

On the properties of the input pattern fault model. - Ronald D. Blanton; John P. Hayes (ACM Trans. Design Autom. Electr. Syst., 2003)

Compact Dictionaries for Diagnosis of Unmodeled Faults in Scan-BIST. - Chunsheng Liu; Kumar N. Dwarakanath; Krishnendu Chakrabarty; Ronald D. Blanton (ISVLSI, 2004)

CAEN-BIST: Testing the NanoFabric. - Jason G. Brown; R. D. (Shawn) Blanton (ITC, 2004)

Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. - Thomas J. Vogels; Thomas Zanon; Rao Desineni; R. D. (Shawn) Blanton; Wojciech Maly; Jason G. Brown; Jeffrey E. Nelson; Y. Fei; X. Huang; Padmini Gopalakrishnan; Mahim Mishra; Vyacheslav Rovner; et al. (ITC, 2004)

Generalized Sensitization using Fault Tuples. - Sounil Biswas; Kumar N. Dwarakanath; R. D. (Shawn) Blanton (VTS, 2004)

Multi-Modal Built-In Self-Test for Symmetric Microsystems. - Nilmoni Deb; R. D. (Shawn) Blanton (VTS, 2004)

Specification Test Compaction for Analog Circuits and MEMS. - Sounil Biswas; Peng Li 001; R. D. (Shawn) Blanton; Larry T. Pileggi (DATE, 2005)

Testing Nanometer Digital Integration Circuits: Myths, Reality and the Road Ahead. - R. D. (Shawn) Blanton; Subhasish Mitra (VLSI Design, 2005)

Diagnosis of Arbitrary Defects Using Neighborhood Function Extraction. - Rao Desineni; R. D. (Shawn) Blanton (VTS, 2005)

Multiple-detect ATPG based on physical neighborhoods. - Jeffrey E. Nelson; Jason G. Brown; Rao Desineni; R. D. (Shawn) Blanton (DAC, 2006)

Extraction of defect density and size distributions from wafer sort test results. - Jeffrey E. Nelson; Thomas Zanon; Rao Desineni; Jason G. Brown; N. Patil; Wojciech Maly; R. D. (Shawn) Blanton (DATE, 2006)

Diagnostic Test Generation for Arbitrary Faults. - Naresh K. Bhatti; Ronald D. Blanton (ITC, 2006)

A Logic Diagnosis Methodology for Improved Localization and Extraction of Accurate Defect Behavior. - Rao Desineni; Osei Poku; Ronald D. Blanton (ITC, 2006)

Exploiting Regularity for Inductive Fault Analysis. - Jason G. Brown; R. D. (Shawn) Blanton (VTS, 2006)

Statistical Test Compaction Using Binary Decision Trees. - Sounil Biswas; Ronald D. Blanton (IEEE Des. Test Comput., 2006)

Extracting Defect Density and Size Distributions from Product ICs. - Jeffrey E. Nelson; Thomas Zanon; Jason G. Brown; Osei Poku; R. D. (Shawn) Blanton; Wojciech Maly; Brady Benware; Chris Schuermyer (IEEE Des. Test Comput., 2006)

Defect Modeling Using Fault Tuples. - Ronald D. Blanton; Kumar N. Dwarakanath; Rao Desineni (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Inductive fault analysis of surface-micromachined MEMS. - Tao Jiang 028; R. D. (Shawn) Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Delay defect diagnosis using segment network faults. - Osei Poku; Ronald D. Blanton (ITC, 2007)

A Built-in Self-test and Diagnosis Strategy for Chemically Assembled Electronic Nanotechnology. - Jason G. Brown; R. D. (Shawn) Blanton (J. Electron. Test., 2007)

Precise failure localization using automated layout analysis of diagnosis candidates. - Wing Chiu Tam; Osei Poku; R. D. (Shawn) Blanton (DAC, 2008)

Multiple defect diagnosis using no assumptions on failing pattern characteristics. - Xiaochun Yu; R. D. (Shawn) Blanton (DAC, 2008)

Automated Testability Enhancements for Logic Brick Libraries. - Jason G. Brown; Brian Taylor; Ronald D. Blanton; Larry T. Pileggi (DATE, 2008)

Physically-Aware N-Detect Test Pattern Selection. - Yen-Tzu Lin; Osei Poku; Naresh K. Bhatti; Ronald D. Blanton (DATE, 2008)

Automated Standard Cell Library Analysis for Improved Defect Modeling. - Jason G. Brown; R. D. (Shawn) Blanton (ISQED, 2008)

Improving the Accuracy of Test Compaction through Adaptive Test Update. - Sounil Biswas; Ronald D. Blanton (ITC, 2008)

Evaluating the Effectiveness of Physically-Aware N-Detect Test using Real Silicon. - Yen-Tzu Lin; Osei Poku; Ronald D. Blanton; Phil Nigh; Peter Lloyd; Vikram Iyengar (ITC, 2008)

An Effective and Flexible Multiple Defect Diagnosis Methodology Using Error Propagation Analysis. - Xiaochun Yu; Ronald D. Blanton (ITC, 2008)

Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. - Sounil Biswas; R. D. (Shawn) Blanton (VTS, 2008)

Automated failure population creation for validating integrated circuit diagnosis methods. - Wing Chiu Tam; Osei Poku; R. D. (Shawn) Blanton (DAC, 2009)

Virtual probe: A statistically optimal framework for minimum-cost silicon characterization of nanoscale integrated circuits. - Xin Li 001; Rob A. Rutenbar; R. D. (Shawn) Blanton (ICCAD, 2009)

Test effectiveness evaluation through analysis of readily-available tester data. - Yen-Tzu Lin; Ronald D. Blanton (ITC, 2009)

Maintaining Accuracy of Test Compaction through Adaptive Re-learning. - Sounil Biswas; Ronald D. Blanton (VTS, 2009)

Physically-Aware N-Detect Test Relaxation. - Yen-Tzu Lin; Chukwuemeka U. Ezekwe; Ronald D. Blanton (VTS, 2009)

Controlling DPPM through Volume Diagnosis. - Xiaochun Yu; Yen-Tzu Lin; Wing Chiu Tam; Osei Poku; Ronald D. Blanton (VTS, 2009)

Automatic classification of bridge defects. - Jeffrey E. Nelson; Wing Chiu Tam; Ronald D. Blanton (ITC, 2010)

Systematic defect identification through layout snippet clustering. - Wing Chiu Tam; Osei Poku; Ronald D. Blanton (ITC, 2010)

Estimating defect-type distributions through volume diagnosis and defect behavior attribution. - Xiaochun Yu; Ronald D. Blanton (ITC, 2010)

Evaluating yield and testing impact of sub-wavelength lithography. - Wing Chiu Tam; R. D. (Shawn) Blanton; Wojciech Maly (VTS, 2010)

Enhancing CMOS Using Nanoelectronic Devices: A Perspective on Hybrid Integrated Systems. - David S. Ricketts; James A. Bain; Yi Luo; Ronald D. Blanton; Kenneth Mai; Gary K. Fedder (Proc. IEEE, 2010)

Diagnosis of Integrated Circuits With Multiple Defects of Arbitrary Characteristics. - Xiaochun Yu; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

To DFM or not to DFM? - Wing Chiu Tam; R. D. (Shawn) Blanton (DAC, 2011)

Statistical defect-detection analysis of test sets using readily-available tester data. - Xiaochun Yu; R. D. (Shawn) Blanton (ICCAD, 2011)

SLIDER: A fast and accurate defect simulation framework. - Wing Chiu Tam; Ronald D. Blanton (VTS, 2011)

Reducing Test Execution Cost of Integrated, Heterogeneous Systems Using Continuous Test Data. - Sounil Biswas; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

METER: Measuring Test Effectiveness Regionally. - Yen-Tzu Lin; R. D. (Shawn) Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Virtual Probe: A Statistical Framework for Low-Cost Silicon Characterization of Nanoscale Integrated Circuits. - Wangyang Zhang; Xin Li 001; Frank Liu 001; Emrah Acar; Rob A. Rutenbar; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

Test-data volume optimization for diagnosis. - Hongfei Wang; Osei Poku; Xiaochun Yu; Sizhe Liu; Ibrahima Komara; Ronald D. Blanton (DAC, 2012)

On-chip diagnosis for early-life and wear-out failures. - Matthew Beckler; R. D. (Shawn) Blanton (ITC, 2012)

Yield Learning Through Physically Aware Diagnosis of IC-Failure Populations. - R. D. (Shawn) Blanton; Wing Chiu Tam; Xiaochun Yu; Jeffrey E. Nelson; Osei Poku (IEEE Des. Test Comput., 2012)

Physically-Aware Analysis of Systematic Defects in Integrated Circuits. - Wing Chiu Tam; Ronald D. Blanton (IEEE Des. Test Comput., 2012)

Physically-Aware N-Detect Test. - Yen-Tzu Lin; Osei Poku; R. D. (Shawn) Blanton; Phil Nigh; Peter Lloyd; Vikram Iyengar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

SLIDER: Simulation of Layout-Injected Defects for Electrical Responses. - Wing Chiu Tam; R. D. (Shawn) Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Diagnosis-Assisted Adaptive Test. - Xiaochun Yu; R. D. (Shawn) Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

Improving Diagnosis Through Failing Behavior Identification. - Xiaochun Yu; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012)

DREAMS: DFM rule EvAluation using manufactured silicon. - Ronald D. Blanton; Fa Wang; Cheng Xue; Pranab K. Nag; Yang Xue; Xin Li 001 (ICCAD, 2013)

SCAN-PUF: A low overhead Physically Unclonable Function from scan chain power-up states. - Ben Niewenhuis; Ronald D. Blanton; Mudit Bhargava; Ken Mai (ITC, 2013)

PADRE: Physically-Aware Diagnostic Resolution Enhancement. - Yang Xue; Osei Poku; Xin Li 001; Ronald D. Blanton (ITC, 2013)

Special session 4B: Elevator talks. - Jennifer Dworak; Ronald Shawn Blanton; Masahiro Fujita; Kazumi Hatayama; Naghmeh Karimi; Michail Maniatakos; Antonis M. Paschalis; Adit D. Singh; Tian Xia (VTS, 2013)

Physically-Aware Diagnostic Resolution. - John A. Porche; R. D. (Shawn) Blanton (ATS, 2014)

Predicting IC Defect Level Using Diagnosis. - Cheng Xue; R. D. (Shawn) Blanton (ATS, 2014)

Ultra-low-power biomedical circuit design and optimization: Catching the don't cares. - Xin Li 001; Ronald Shawn Blanton; Pulkit Grover; Donald E. Thomas (ISIC, 2014)

SLIC: Statistical learning in chip. - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ISIC, 2014)

Logic characterization vehicle design for maximal information extraction for yield learning. - Ronald D. Blanton; Ben Niewenhuis; Carl Taylor (ITC, 2014)

Bayesian model fusion: Enabling test cost reduction of analog/RF circuits via wafer-level spatial variation modeling. - Shanghang Zhang; Xin Li 001; Ronald D. Blanton; José Machado da Silva; John M. Carulli Jr.; Kenneth M. Butler (ITC, 2014)

Design-for-Manufacturability Assessment for Integrated Circuits Using RADAR. - Wing Chiu Tam; R. D. (Shawn) Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Reducing test cost of integrated, heterogeneous systems using pass-fail test data analysis. - Sounil Biswas; Hongfei Wang; R. D. (Shawn) Blanton (ACM Trans. Design Autom. Electr. Syst., 2014)

Detection of illegitimate access to JTAG via statistical learning in chip. - Xuanle Ren; Vítor Grade Tavares; R. D. (Shawn) Blanton (DATE, 2015)

Statistical Learning in Chip (SLIC). - Ronald D. Blanton; Xin Li 001; Ken Mai; Diana Marculescu; Radu Marculescu; Jeyanandh Paramesh; Jeff G. Schneider; Donald E. Thomas (ICCAD, 2015)

A one-pass test-selection method for maximizing test coverage. - Cheng Xue; R. D. (Shawn) Blanton (ICCD, 2015)

Design reflection for optimal test-chip implementation. - R. D. (Shawn) Blanton; Benjamin Niewenhuis; Zeye (Dexter) Liu (ITC, 2015)

Special session: Hot topics: Statistical test methods. - Manuel J. Barragán; Gildas Léger; Florence Azaïs; Ronald D. Blanton; Adit D. Singh; Stephen Sunter (VTS, 2015)

Efficient built-in self test of regular logic characterization vehicles. - Ben Niewenhuis; Ronald D. Blanton (VTS, 2015)

Improving accuracy of on-chip diagnosis via incremental learning. - Xuanle Ren; Mitchell Martin; Ronald D. Blanton (VTS, 2015)

LASIC: Layout Analysis for Systematic IC-Defect Identification Using Clustering. - Wing Chiu Jason Tam; Ronald Shawn Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Achieving 100% cell-aware coverage by design. - Zeye Liu 001; Ben Niewenhuis; Soumya Mittal; R. D. (Shawn) Blanton (DATE, 2016)

A Learning-Based Approach to Secure JTAG Against Unseen Scan-Based Attacks. - Xuanle Ren; Ronald D. Blanton; Vítor Grade Tavares (ISVLSI, 2016)

Logic characterization vehicle design reflection via layout rewiring. - Phillip Fynan; Zeye Liu 001; Benjamin Niewenhuis; Soumya Mittal; Marcin Strajwas; R. D. (Shawn) Blanton (ITC, 2016)

Diagnostic resolution improvement through learning-guided physical failure analysis. - Carlston Lim; Yang Xue; Xin Li 001; Ronald D. Blanton; M. Enamul Amyeen (ITC, 2016)

Test chip design for optimal cell-aware diagnosability. - Soumya Mittal; Zeye Liu 001; Ben Niewenhuis; R. D. (Shawn) Blanton (ITC, 2016)

Test: Wisdom From the Giants, Visions for the Future - Part 2. - R. D. Shawn Blanton; David Yeh (IEEE Des. Test, 2016)

Ensemble Reduction via Logic Minimization. - Hongfei Wang; R. D. (Shawn) Blanton (ACM Trans. Design Autom. Electr. Syst., 2016)

PADLOC: Physically-Aware Defect Localization and Characterization. - Soumya Mittal; R. D. (Shawn) Blanton (ATS, 2017)

Partial co-training for virtual metrology. - Cuong Nguyen; Xin Li 001; Ronald Shawn Blanton; Xiang Li 040 (ETFA, 2017)

Multiple-defect diagnosis for Logic Characterization Vehicles. - Ben Niewenhuis; Soumya Mittal; R. D. (Shawn) Blanton (ETS, 2017)

LightNN: Filling the Gap between Conventional Deep Neural Networks and Binarized Networks. - Ruizhou Ding; Zeye Liu 001; Rongye Shi; Diana Marculescu; R. D. (Shawn) Blanton (ACM Great Lakes Symposium on VLSI, 2017)

Random Forest Architectures on FPGA for Multiple Applications. - Xiang Lin; R. D. (Shawn) Blanton; Donald E. Thomas (ACM Great Lakes Symposium on VLSI, 2017)

GPU-accelerated fault dictionary generation for the TRAX fault model. - Matthew Beckler; R. D. Shawn Blanton (ITC-Asia, 2017)

Fault simulation acceleration for TRAX dictionary construction using GPUs. - Matthew Beckler; Ronald D. Blanton (ITC, 2017)

Front-end layout reflection for test chip design. - Zeye Liu 001; Phillip Fynan; Ronald D. Blanton (ITC, 2017)

Test-set reordering for improving diagnosability. - Cheng Xue; R. D. (Shawn) Blanton (VTS, 2017)

DFM Evaluation Using IC Diagnosis Data. - Ronald Shawn Blanton; Fa Wang; Cheng Xue; Pranab K. Nag; Yang Xue; Xin Li 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017)

Quantized deep neural networks for energy efficient hardware-based inference. - Ruizhou Ding; Zeye Liu 001; R. D. (Shawn) Blanton; Diana Marculescu (ASP-DAC, 2018)

CompactNet: High Accuracy Deep Neural Network Optimized for On-Chip Implementation. - Abhinav Goel; Zeye Liu 001; Ronald D. Blanton (IEEE BigData, 2018)

Detection of IJTAG attacks using LDPC-based feature reduction and machine learning. - Xuanle Ren; R. D. (Shawn) Blanton; Vítor Grade Tavares (ETS, 2018)

Back-End Layout Reflection for Test Chip Design. - Zeye Liu 001; Ronald D. Blanton (ICCD, 2018)

Improving Diagnosis Efficiency via Machine Learning. - Qicheng Huang; Chenlei Fang; Soumya Mittal; R. D. Shawn Blanton (ITC, 2018)

NOIDA: Noise-resistant Intra-cell Diagnosis. - Soumya Mittal; R. D. (Shawn) Blanton (VTS, 2018)

Improving Diagnostic Resolution of Failing ICs Through Learning. - Yang Xue; Xin Li 001; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Lightening the Load with Highly Accurate Storage- and Energy-Efficient LightNNs. - Ruizhou Ding; Zeye Liu 001; R. D. (Shawn) Blanton; Diana Marculescu (ACM Trans. Reconfigurable Technol. Syst., 2018)

FLightNNs: Lightweight Quantized Deep Neural Networks for Fast and Accurate Inference. - Ruizhou Ding; Zeye Liu 001; Ting-Wu Chin; Diana Marculescu; R. D. (Shawn) Blanton (DAC, 2019)

LearnX: A Hybrid Deterministic-Statistical Defect Diagnosis Methodology. - Soumya Mittal; R. D. Shawn Blanton (ETS, 2019)

IPSA: Integer Programming via Sparse Approximation for Efficient Test-Chip Design. - Qicheng Huang; Chenlei Fang; Zeye Liu 001; Ruizhou Ding; R. D. Shawn Blanton (ICCD, 2019)

Characterization of Locked Sequential Circuits via ATPG. - Danielle Duvalsaint; Zeye Liu 001; Ananya Ravikumar; Ronald D. Blanton (ITC-Asia, 2019)

Characterization of Locked Combinational Circuits via ATPG. - Danielle Duvalsaint; Xiaoxiao Jin; Benjamin Niewenhuis; R. D. (Shawn) Blanton (ITC, 2019)

Improving Test Chip Design Efficiency via Machine Learning. - Zeye Liu 001; Qicheng Huang; Chenlei Fang; R. D. (Shawn) Blanton (ITC, 2019)

Diagnosis Outcome Preview through Learning. - Chenlei Fang; Qicheng Huang; Soumya Mittal; R. D. Shawn Blanton (VTS, 2019)

Path Delay Test of the Carnegie Mellon Logic Characterization Vehicle. - Ben Niewenhuis; Balaji Ravikumar; Zeye Liu 001; R. D. Shawn Blanton (VTS, 2019)

On-Chip Diagnosis of Generalized Delay Failures Using Compact Fault Dictionaries. - Matthew Layne Beckler; Ronald D. Blanton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

IC Protection Against JTAG-Based Attacks. - Xuanle Ren; Francisco Pimentel Torres; Ronald D. Blanton; Vítor Grade Tavares (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

DECOY: DEflection-Driven HLS-Based Computation Partitioning for Obfuscating Intellectual PropertY. - Jianqi Chen; Monir Zaman; Yiorgos Makris; R. D. Shawn Blanton; Subhasish Mitra; Benjamin Carrión Schäfer (DAC, 2020)

Efficient Classification via Partial Co-Training for Virtual Metrology. - Cuong Nguyen; Xin Li 001; R. D. Shawn Blanton; Xiang Li 001 (ETFA, 2020)

Design Obfuscation versus Test. - Farimah Farahmandi; Ozgur Sinanoglu; Ronald D. Blanton; Samuel Pagliarini (ETS, 2020)

Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors. - Chenlei Fang; Qicheng Huang; R. D. Shawn Blanton (ITC-Asia, 2020)

Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest. - Qicheng Huang; Chenlei Fang; R. D. Shawn Blanton (ITC-Asia, 2020)

High Defect-Density Yield Learning using Three-Dimensional Logic Test Chips. - Zeye Liu 001; R. D. Shawn Blanton (ITC, 2020)

LAIDAR: Learning for Accuracy and Ideal Diagnostic Resolution. - Qicheng Huang; Chenlei Fang; R. D. Shawn Blanton (ITC, 2020)

Knowledge Transfer for Diagnosis Outcome Preview with Limited Data. - Qicheng Huang; Chenlei Fang; R. D. Shawn Blanton (ITC, 2020)

Special Session: Novel Attacks on Logic-Locking. - Ayush Jain 002; Ujjwal Guin; M. Tanjidur Rahman; Navid Asadizanjani; Danielle Duvalsaint; R. D. Shawn Blanton (VTS, 2020)

A Deterministic-Statistical Multiple-Defect Diagnosis Methodology. - Soumya Mittal; R. D. Shawn Blanton (VTS, 2020)

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking. - Benjamin Tan 001; Ramesh Karri; Nimisha Limaye; Abhrajit Sengupta; Ozgur Sinanoglu; Md. Moshiur Rahman 001; Swarup Bhunia; Danielle Duvalsaint; Ronald D. Blanton; Amin Rezaei 001; Yuanqi Shen; Hai Zhou 001; et al. (CoRR, 2020)

CircuitGraph: A Python package for Boolean circuits. - Joseph Sweeney; Ruben Purdy; Ronald D. Blanton; Lawrence T. Pileggi (J. Open Source Softw., 2020)

Partial Bayesian Co-training for Virtual Metrology. - Cuong Manh Nguyen; Xin Li 001; Ronald DeShawn Blanton; Xiang Li 040 (IEEE Trans. Ind. Informatics, 2020)

Towards Smarter Diagnosis: A Learning-based Diagnostic Outcome Previewer. - Qicheng Huang; Chenlei Fang; Soumya Mittal; R. D. (Shawn) Blanton (ACM Trans. Design Autom. Electr. Syst., 2020)

Characterizing Corruptibility of Logic Locks using ATPG. - Danielle Duvalsaint; R. D. Shawn Blanton (ITC, 2021)

AAA: Automated, On-ATE AI Debug of Scan Chain Failures. - Chris Nigh; Gaurav Bhargava; Ronald D. Blanton (ITC, 2021)

Memory-Efficient Adaptive Test Pattern Reordering for Accurate Diagnosis. - Chenlei Fang; Qicheng Huang; R. D. Shawn Blanton (VTS, 2021)

Split-Chip Design to Prevent IP Reverse Engineering. - Samuel Pagliarini; Joseph Sweeney; Ken Mai; R. D. Shawn Blanton; Larry T. Pileggi; Subhasish Mitra (IEEE Des. Test, 2021)

Secuirty Metrics for Logic Circuits. - Ruben Purdy; Danielle Duvalsaint; R. D. Shawn Blanton (HOST, 2022)

Large-Scale Logic-Locking Attacks via Simulation. - Ruben Purdy; R. D. Shawn Blanton (ISQED, 2022)

PEPR: Pseudo-Exhaustive Physically-Aware Region Testing. - Wei Li; Chris Nigh; Danielle Duvalsaint; Subhasish Mitra; Ronald D. Blanton (ITC, 2022)

Global Floorplanning via Semidefinite Programming. - Wei Li; Fangzhou Wang; José M. F. Moura; R. D. (Shawn) Blanton (DAC, 2023)

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. - Prabhu Vellaisamy; Harideep Nair; Joseph Finn; Manav Trivedi; Albert Chen 002; Anna Li; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (ISVLSI, 2023)

Characterize the ability of GNNs in attacking logic locking. - Wei Li; Ruben Purdy; José M. F. Moura; R. D. Shawn Blanton (MLCAD, 2023)

Efficient Test Chip Design via Smart Computation. - Chenlei Fang; Qicheng Huang; Zeye Liu 001; Ruizhou Ding; Ronald D. Blanton (ACM Trans. Design Autom. Electr. Syst., 2023)

Silent Data Corruption: Test or Reliability Problem? - Erik Jan Marinissen; Harish Dattatraya Dixit; Ronald Shawn Blanton; Aaron Kuo; Wei Li; Subhasish Mitra; Chris Nigh; Ruben Purdy; Ben Kaczer; Dishant Sangani; Pieter Weckx; Philippe J. Roussel; et al. (ETS, 2024)

Faulty Function Extraction for Defective Circuits. - Chris Nigh; Ruben Purdy; Wei Li; Subhasish Mitra; R. D. Shawn Blanton (ETS, 2024)

Exploration of Unary Arithmetic-Based Matrix Multiply Units for Low Precision DL Accelerators. - Prabhu Vellaisamy; Harideep Nair; Di Wu; R. D. Shawn Blanton; John Paul Shen (ISVLSI, 2024)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (VLSI-SoC, 2024)

Logic-AAA: Debug of Logic Failures with an on-ATE Expert System. - Chris Nigh; Ronald D. Blanton (VTS, 2024)

OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (CoRR, 2024)

Tempus Core: Area-Power Efficient Temporal-Unary Convolution Core for Low-Precision Edge DLAs. - Prabhu Vellaisamy; Harideep Nair; Thomas Kang; Yichen Ni; Haoyang Fan; Bin Qi; Jeff Chen; R. D. Shawn Blanton; John Paul Shen (DATE, 2025)

CHEF: CHaracterizing Elusive Logic Circuit Failures. - Ruben Purdy; Chris Nigh; Wei Li; R. D. Shawn Blanton (VTS, 2025)

BRIDGES: Bridging Graph Modality and Large Language Models within EDA Tasks. - Wei Li; Yang Zou; Christopher Ellis; Ruben Purdy; R. D. (Shawn) Blanton; José M. F. Moura (CoRR, 2025)