A 576 K 3.5-ns access BiCMOS ECL static RAM with array built-in self-test. - Henry A. Bonges III; R. Dean Adams; Archibald J. Allen; Roy Flaker; Kenneth S. Gray; Erik L. Hedberg; W. Timothy Holman; George M. Lattimore; David A. Lavalette; Kim Yen T. Nguyen; Alan L. Roberts (IEEE J. Solid State Circuits, 1992)

A 370-MHz memory built-in self-test state machine. - R. Dean Adams; John Connor; Garret S. Koch; Luigi Ternullo Jr. (ED&TC, 1995)

Deterministic Self-Test of a High-Speed Embedded Memory and Logic Processor Subsystem. - Luigi Ternullo Jr.; R. Dean Adams; John Connor; Garret S. Koch (ITC, 1995)

A Self-Test Circuit for Evaluating Memory Sense-Amplifier Signal. - R. Dean Adams; Edmond S. Cooley; Patrick R. Hansen (ITC, 1997)

Quad DCVS dynamic logic fault modeling and testing. - R. Dean Adams; Edmond S. Cooley; Patrick R. Hansen (ITC, 1998)

The Limits of Digital Testing for Dynamic Circuits. - R. Dean Adams; Edmond S. Cooley (VTS, 1999)

Self test architecture for testing complex memory structures. - Kamran Zarrineh; R. Dean Adams; Thomas J. Eckenrode; Steven P. Gregor (ITC, 2000)

Defect Analysis and Realistic Fault Model Extensions for Static Random Access Memories. - Kamran Zarrineh; R. Dean Adams; Aneesha P. Deo (MTDT, 2000)

Silicon-on-Insulator Technology Impacts on SRAM Testing. - R. Dean Adams; Phil Shephard III (VTS, 2000)

Defect Analysis and a New Fault Model for Multi-port SRAMs. - Pradeep Nagaraj; Shambhu Upadhaya; Kamran Zarrineh; R. Dean Adams (DFT, 2001)

Bitline contacts in high density SRAMs: design for testability and stressability. - Harold Pilo; R. Dean Adams; Robert E. Busch; Eric A. Nelson; Geoerge E. Rudgers (ITC, 2001)

Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. - Robert Gibbins; R. Dean Adams; Thomas J. Eckenrode; Michael Ouellette; Yuejian Wu (MTDT, 2002)

An Integrated Memory Self Test and EDA Solution. - R. Dean Adams; Robert Abbott; Xiaoliang Bai; Dwayne Burek; Eric MacDonald (MTDT, 2004)