Luke R. Everson
Orcid: 0000-0002-1209-0395
According to our database1,
Luke R. Everson
authored at least 13 papers
between 2015 and 2022.
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Bibliography
2022
An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process.
IEEE J. Solid State Circuits, 2022
2021
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses.
IEEE Trans. Very Large Scale Integr. Syst., 2021
A Time-Based Intra-Memory Computing Graph Processor Featuring A* Wavefront Expansion and 2-D Gradient Control.
IEEE J. Solid State Circuits, 2021
2019
CorNET: Deep Learning Framework for PPG-Based Heart Rate Estimation and Biometric Identification in Ambulant Environment.
IEEE Trans. Biomed. Circuits Syst., 2019
An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm.
IEEE J. Solid State Circuits, 2019
A 40×40 Four-Neighbor Time-Based In-Memory Computing Graph ASIC Chip Featuring Wavefront Expansion and 2D Gradient Control.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
2018
A Physical Unclonable Function based on Capacitor Mismatch in a Charge-Redistribution SAR-ADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
A 0.0094mm<sup>2</sup>/Channel Time-Based Beat Frequency ADC in 65nm CMOS for Intra-Electrode Neural Recording.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018
A 104.8TOPS/W One-Shot Time-Based Neuromorphic Chip Employing Dynamic Threshold Error Correction in 65nm.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A scalable time-based integrate-and-fire neuromorphic core with brain-inspired leak and local lateral inhibition capabilities.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2015
Design space exploration for efficient computing in Solid State drives with the Storage Processing Unit.
Proceedings of the 10th IEEE International Conference on Networking, 2015