Design and Performance Evaluation of EXMAN: An EXtended MANchester Data Flow Computer. - Lalit M. Patnaik; R. Govindarajan; N. S. Ramadoss (IEEE Trans. Computers, 1986)

PROMIDS: A PROtotype multi-rIng data flow system for functional programming languages. - R. Govindarajan; R. Kumar; D. Kumar; L. M. Patnaik (Microprocessing and Microprogramming, 1989)

Lenient Execution and Concurrent Execution of Re-Entrant Routines: Efficient Implementation in Data Flow Systems. - R. Govindarajan; Lalit M. Patnaik (Comput. J., 1990)

ParC project: practical constructs for parallel programming languages. - R. Govindarajan; Lifu Guo; Sheng Yu 001; P. Wang (COMPSAC, 1991)

Data Flow Implementation of Generalized Guarded Commands. - R. Govindarajan; Sheng Yu 001 (PARLE (1), 1991)

Software fault-tolerance in functional programming. - R. Govindarajan (COMPSAC, 1992)

A Large Context Multithreaded Architecture. - Ramaswamy Govindarajan; Shashank S. Nemawarkar (CONPAR, 1992)

Well-behaved dataflow programs for DSP computation. - Guang R. Gao; R. Govindarajan; Prakash Panangaden (ICASSP, 1992)

Performance Evaluation of Latency Tolerant Architectures. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (ICCI, 1992)

Exploiting instruction-level parallelism: the multithreaded approach. - Philip LeNir; Ramaswamy Govindarajan; Shashank S. Nemawarkar (MICRO, 1992)

SMALL: A Scalable Multithreaded Architecture to Exploit Large Localiy. - Ramaswamy Govindarajan; Shashank S. Nemawarkar (SPDP, 1992)

Attempting guards in parallel: A data flow approach to execute generalized guarded commands. - R. Govindarajan; Sheng Yu 001; V. S. Lakshmanan 001 (Int. J. Parallel Program., 1992)

A novel framework for multi-rate scheduling in DSP applications. - R. Govindarajan; Guang R. Gao (ASAP, 1993)

Analysis of Multithreaded Multiprocessors with Distributed Shared Memory. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (SPDP, 1993)

Exception Handlers in Functional Programming Languages. - R. Govindarajan (IEEE Trans. Software Eng., 1993)

Minimizing memory requirements in rate-optimal schedules. - Ramaswamy Govindarajan; Guang R. Gao; Palash Desai (ASAP, 1994)

Minimizing register requirements under resource-constrained rate-optimal software pipelining. - Ramaswamy Govindarajan; Erik R. Altman; Guang R. Gao (MICRO, 1994)

Performance of Interconnection Network in Multithreaded Architectures. - Shashank S. Nemawarkar; Ramaswamy Govindarajan; Guang R. Gao; Vinod K. Agarwal (PARLE, 1994)

Design and Performance Evaluation of a Multithreaded Architecture. - Ramaswamy Govindarajan; Shashank S. Nemawarkar; Philip LeNir (HPCA, 1995)

An Experimental Study of an ILP-based Exact Solution Method for Software Pipelining. - Erik R. Altman; Guang R. Gao; Ramaswamy Govindarajan (LCPC, 1995)

Scheduling and Mapping: Software Pipelining in the Presence of Structural Hazards. - Erik R. Altman; Ramaswamy Govindarajan; Guang R. Gao (PLDI, 1995)

Rate-optimal schedule for multi-rate DSP computations. - Ramaswamy Govindarajan; Guang R. Gao (J. VLSI Signal Process., 1995)

Buffer allocation in regular dataflow networks: an approach based on coloring circular-arc graphs. - Ramaswamy Govindarajan; S. Rengarajan (HiPC, 1996)

Co-Scheduling Hardware and Software Pipelines. - Ramaswamy Govindarajan; Erik R. Altman; Guang R. Gao (HPCA, 1996)

A Framework for Resource-Constrained Rate-Optimal Software Pipelining. - Ramaswamy Govindarajan; Erik R. Altman; Guang R. Gao (IEEE Trans. Parallel Distributed Syst., 1996)

A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors. - Rad Silvera; Jian Wang 046; Ramaswamy Govindarajan; Guang R. Gao (IEEE PACT, 1997)

Classification and performance evaluation of simultaneous multithreaded architectures. - B. Hari Krishna; Ramaswamy Govindarajan (HiPC, 1997)

Distributed Shared Memory on IBM SP2. - S. Ramesh; R. Lakshmi 002; R. Govindarajan (ICPADS, 1997)

Timed Petri net models of multithreaded multiprocessor architectures. - R. Govindarajan; F. Suciu; Wlodek M. Zuberek (PNPM, 1997)

Modulo-variable expansion sensitive scheduling. - Madhavi Gopal Valluri; R. Govindarajan (HiPC, 1998)

Register-Sensitive Software Pipelining. - Amod K. Dani; V. Janaki Ramanan; Ramaswamy Govindarajan (IPPS/SPDP, 1998)

An Enhanced Co-Scheduling Method Using Reduced MS-State Diagrams. - Ramaswamy Govindarajan; N. S. S. Narasimha Rao; Erik R. Altman; Guang R. Gao (IPPS/SPDP, 1998)

Performance bounds for distributed memory multithreaded architectures. - Wlodzimierz M. Zuberek; R. Govindarajan (SMC, 1998)

A Unified Framework for Instruction Scheduling and Mapping for Function Units with Structural Hazards. - Erik R. Altman; Ramaswamy Govindarajan; Guang R. Gao (J. Parallel Distributed Comput., 1998)

Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors. - Madhavi Gopal Valluri; R. Govindarajan (IEEE PACT, 1999)

Efficient State-Diagram Construction Methods for Software Pipelining. - Chihong Zhang; Ramaswamy Govindarajan; Sean Ryan; Guang R. Gao (CC, 1999)

Resource Usage Modelling for Software Pipelining. - V. Janaki Ramanan; Ramaswamy Govindarajan (HiPC, 1999)

Resource usage models for instruction scheduling: two new models and a classification. - V. Janaki Ramanan; Ramaswamy Govindarajan (International Conference on Supercomputing, 1999)

Minimum Register Instruction Scheduling: A New Approach for Dynamic Instruction Issue Processors. - Ramaswamy Govindarajan; Chihong Zhang; Guang R. Gao (LCPC, 1999)

A Theory for Software-Hardware Co-Scheduling for ASIPs and Embedded Processors. - Ramaswamy Govindarajan; Erik R. Altman; Guang R. Gao (ASAP, 2000)

Enhanced Co-Scheduling: A Software Pipelining Method Using Modulo-Scheduled Pipeline Theory. - Ramaswamy Govindarajan; N. S. S. Narasimha Rao; Erik R. Altman; Guang R. Gao (Int. J. Parallel Program., 2000)

A Vectorizing Compiler for Multimedia Extensions. - N. Sreraman; R. Govindarajan (Int. J. Parallel Program., 2000)

Hidden Costs in Avoiding False Sharing in Software DSMs. - K. V. Manjunath; R. Govindarajan (HiPC, 2001)

Minimum Register Instruction Sequence Problem: Revisiting Optimal Code Generation for DAGs. - Ramaswamy Govindarajan; Hongbo Yang; Chihong Zhang; José Nelson Amaral; Guang R. Gao (IPDPS, 2001)

Guest Editors' Introduction: Special Issue on Cluster and Network-Based Computing. - Ramaswamy Govindarajan; Anand Sivasubramaniam (J. Parallel Distributed Comput., 2001)

Instruction Scheduling. - Ramaswamy Govindarajan (The Compiler Design Handbook, 2002)

Dynamic Path Profile Aided Recompilation in a JAVA Just-In-Time Compiler. - R. Vinodh Kumar; B. Lakshmi Narayanan; R. Govindarajan (HiPC, 2002)

Power-Performance Trade-Offs for Energy-Efficient Architectures: A Quantitative Study. - Hongbo Yang; Ramaswamy Govindarajan; Guang R. Gao; Kevin B. Theobald (ICCD, 2002)

A Theory for Co-Scheduling Hardware and Software Pipelines in ASIPs and Embedded Processors. - R. Govindarajan; Erik R. Altman; Guang R. Gao (Des. Autom. Embed. Syst., 2002)

Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks. - Ramaswamy Govindarajan; Guang R. Gao; Palash Desai (J. VLSI Signal Process., 2002)

An Efficient Web Cache Replacement Policy. - A. Radhika Sarma; R. Govindarajan (HiPC, 2003)

Exploiting Java-ILP on a Simultaneous Multi-Trace Instruction Issue (SMTI) Processor. - R. Achutharaman; R. Govindarajan; G. Hariprakash; Amos Omondi (IPDPS, 2003)

Programming Models and System Software for Future High-End Computing Systems: Work-in-Progress. - Guang R. Gao; Kevin B. Theobald; Ramaswamy Govindarajan; Clement Leung; Ziang Hu; Haiping Wu; Jizhu Lu; Juan del Cuvillo; Adeline Jacquet; Vincent Janot; Thomas L. Sterling (IPDPS, 2003)

An Executable Analytical Performance Evaluation Approach for Early Performance Prediction. - Adeline Jacquet; Vincent Janot; Clement Leung; Guang R. Gao; Ramaswamy Govindarajan; Thomas L. Sterling (IPDPS, 2003)

Compiler-Assisted Cache Replacement: Problem Formulation and Performance Evaluation. - Hongbo Yang; Ramaswamy Govindarajan; Guang R. Gao; Ziang Hu (LCPC, 2003)

Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. - V. V. N. S. Sarvani; R. Govindarajan (SCOPES, 2003)

Optimal Code and Data Layout in Embedded Systems. - T. S. Rajesh Kumar; R. Govindarajan; C. P. Ravikumar (VLSI Design, 2003)

Minimum Register Instruction Sequencing to Reduce Register Spills in Out-of-Order Issue Superscalar Architectures. - Ramaswamy Govindarajan; Hongbo Yang; José Nelson Amaral; Chihong Zhang; Guang R. Gao (IEEE Trans. Computers, 2003)

Code Generation for Single-Dimension Software Pipelining of Multi-Dimensional Loops. - Hongbo Rong; Alban Douillet; Ramaswamy Govindarajan; Guang R. Gao (CGO, 2004)

Single-Dimension Software Pipelining for Multi-Dimensional Loops. - Hongbo Rong; Zhizhong Tang; Ramaswamy Govindarajan; Alban Douillet; Guang R. Gao (CGO, 2004)

CAS-DSM: A Compiler Assisted Software Distributed Shared Memory. - N. P. Manoj; K. V. Manjunath; R. Govindarajan (Int. J. Parallel Program., 2004)

Performance analysis of methods that overcome false sharing effects in software DSMs. - Manjunath Kudlur; R. Govindarajan (J. Parallel Distributed Comput., 2004)

Offloading Bloom Filter Operations to Network Processor for Parallel Query Processing in Cluster of Workstations. - V. Santhosh Kumar; Matthew J. Thazhuthaveetil; R. Govindarajan (HiPC, 2005)

A heterogeneously segmented cache architecture for a packet forwarding engine. - Kaushik Rajan; Ramaswamy Govindarajan (ICS, 2005)

Performance Modeling and Architecture Exploration of Network Processors. - S. Govind; R. Govindarajan (QEST, 2005)

Improving power efficiency with compiler-assisted cache replacement. - Hongbo Yang; Ramaswamy Govindarajan; Guang R. Gao; Ziang Hu (J. Embed. Comput., 2005)

Two-level mapping based cache index selection for packet forwarding engines. - Kaushik Rajan; Ramaswamy Govindarajan (PACT, 2006)

A scalable low power issue queue for large instruction window processors. - Rajesh Vivekanandham; Bharadwaj S. Amrutur; R. Govindarajan (ICS, 2006)

Exploiting programmable network interfaces for parallel query execution in workstation clusters. - V. Santhosh Kumar; Matthew J. Thazhuthaveetil; R. Govindarajan (IPDPS, 2006)

Area and Power Reduction of Embedded DSP Systems using Instruction Compression and Re-configurable Encoding. - Subash Chandar G.; Mahesh Mehendale; R. Govindarajan (J. VLSI Signal Process., 2006)

Instruction Scheduling. - R. Govindarajan (The Compiler Design Handbook, 2nd ed., 2007)

Advances in Software Pipelining. - Hongbo Rong; R. Govindarajan (The Compiler Design Handbook, 2nd ed., 2007)

Dynamic Cache Placement with Two-level Mapping to Reduce Conflict Misses. - Kaushik Rajan; Ramaswamy Govindarajan; Bharadwaj Amrutur (PACT, 2007)

A Scalable Low Power Store Queue for Large InstructionWindow Processors. - Rajesh Vivekanandham; R. Govindarajan (PACT, 2007)

MODLEX: A Multi Objective Data Layout EXploration Framework for Embedded Systems-on-Chip. - T. S. Rajesh Kumar; C. P. Ravikumar; R. Govindarajan (ASP-DAC, 2007)

Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation. - Santosh Nagarakatte; R. Govindarajan (CC, 2007)

An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures. - K. Shyam; R. Govindarajan (CC, 2007)

Compiler-Directed Dynamic Voltage Scaling Using Program Phases. - K. Shyam; R. Govindarajan (HiPC, 2007)

Packet Reordering in Network Processors. - S. Govind; R. Govindarajan; Joy Kuri (IPDPS, 2007)

Emulating Optimal Replacement with a Shepherd Cache. - Kaushik Rajan; Ramaswamy Govindarajan (MICRO, 2007)

A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor. - Girish B. C.; R. Govindarajan (QEST, 2007)

MAX: A Multi Objective Memory Architecture eXploration Framework for Embedded Systems-on-Chip. - T. S. Rajesh Kumar; C. P. Ravikumar; R. Govindarajan (VLSI Design, 2007)

FEADS: A Framework for Exploring the Application Design Space on Network Processors. - Rajani Pai; R. Govindarajan (Int. J. Parallel Program., 2007)

Single-dimension software pipelining for multidimensional loops. - Hongbo Rong; Zhizhong Tang; Ramaswamy Govindarajan; Alban Douillet; Guang R. Gao (ACM Trans. Archit. Code Optim., 2007)

Comprehensive path-sensitive data-flow analysis. - Aditya V. Thakur; R. Govindarajan (CGO, 2008)

Improving Performance of Digest Caches in Network Processors. - Girish Chandramohan; Ramaswamy Govindarajan (HiPC, 2008)

Focused prefetching: performance oriented prefetching based on commit stalls. - R. Manikantan; R. Govindarajan (ICS, 2008)

Online unsupervised pattern discovery in speech using parallelization. - Mrugesh R. Gajjar; R. Govindarajan; T. V. Sreenivas (INTERSPEECH, 2008)

A systematic approach to synthesis of verification test-suites for modular SoC designs. - Sudhakar Surendran; Rubin A. Parekhji; R. Govindarajan (SoCC, 2008)

Memory Architecture Exploration Framework for Cache Based Embedded SOC. - T. S. Rajesh Kumar; C. P. Ravikumar; R. Govindarajan (VLSI Design, 2008)

Impact of message compression on the scalability of an atmospheric modeling application on clusters. - V. Santhosh Kumar; Ravi S. Nanjundiah; Matthew J. Thazhuthaveetil; R. Govindarajan (Parallel Comput., 2008)

Region Based Structure Layout Optimization by Selective Data Copying. - Sandya S. Mannarswamy; Ramaswamy Govindarajan; Rishi Surendran (PACT, 2009)

Scalable Context-Sensitive Points-to Analysis Using Multi-dimensional Bloom Filters. - Rupesh Nasre; Kaushik Rajan; Ramaswamy Govindarajan; Uday P. Khedker (APLAS, 2009)

Software Pipelined Execution of Stream Programs on GPUs. - Abhishek Udupa; R. Govindarajan; Matthew J. Thazhuthaveetil (CGO, 2009)

Reducing Buffer Requirements in Core Routers Using Dynamic Buffering. - Girish B. C.; Ramaswamy Govindarajan (ICCCN, 2009)

Synergistic execution of stream programs on multicores with accelerators. - Abhishek Udupa; R. Govindarajan; Matthew J. Thazhuthaveetil (LCTES, 2009)

A Novel Cache Architecture and Placement Framework for Packet Forwarding Engines. - Kaushik Rajan; Ramaswamy Govindarajan (IEEE Trans. Computers, 2009)

NUcache: a multicore cache organization based on next-use distance. - R. Manikantan; Kaushik Rajan; R. Govindarajan (PACT, 2010)

Analyzing cache performance bottlenecks of STM applications and addressing them with compiler's help. - Sandya S. Mannarswamy; Ramaswamy Govindarajan (PACT, 2010)

Handling Conflicts with Compiler's Help in Software Transactional Memory Systems. - Sandya Mannarswamy; R. Govindarajan (ICPP, 2010)

Points-to Analysis as a System of Linear Equations. - Rupesh Nasre; Ramaswamy Govindarajan (SAS, 2010)

Row-Buffer Reorganization: Simultaneously Improving Performance and Reducing Energy in DRAMs. - Nagendra Dwarakanath Gulur; R. Manikantan; R. Govindarajan; Mahesh Mehendale (PACT, 2011)

Making STMs Cache Friendly with Compiler Transformations. - Sandya Mannarswamy; Ramaswamy Govindarajan (PACT, 2011)

Prioritizing constraint evaluation for efficient points-to analysis. - Rupesh Nasre; Ramaswamy Govindarajan (CGO, 2011)

Extended histories: improving regularity and performance in correlation prefetchers. - R. Manikantan; R. Govindarajan; Kaushik Rajan (HiPEAC, 2011)

NUcache: An efficient multicore cache organization based on Next-Use distance. - R. Manikantan; Kaushik Rajan; R. Govindarajan (HPCA, 2011)

Variable Granularity Access Tracking Scheme for Improving the Performance of Software Transactional Memory. - Sandya S. Mannarswamy; Ramaswamy Govindarajan (IPDPS, 2011)

Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors. - Ashwin Prasad; Jayvant Anantpur; R. Govindarajan (PLDI, 2011)

Fast computation of Gaussian likelihoods using low-rank matrix approximations. - Mrugesh R. Gajjar; T. V. Sreenivas; R. Govindarajan (SiPS, 2011)

Performance Oriented Prefetching Enhancements Using Commit Stalls. - R. Manikantan; R. Govindarajan (J. Instr. Level Parallelism, 2011)

Fast and efficient automatic memory management for GPUs using compiler-assisted runtime coherence scheme. - Sreepathi Pai; R. Govindarajan; Matthew J. Thazhuthaveetil (PACT, 2012)

Reconciling transactional conflicts with compiler's help. - Sandya S. Mannarswamy; R. Govindarajan (CGO, 2012)

CUDA-For-Clusters: A System for Efficient Execution of CUDA Kernels on Multi-core Clusters. - Raghu Prabhakar; R. Govindarajan; Matthew J. Thazhuthaveetil (Euro-Par, 2012)

Multiple sub-row buffers in DRAM: unlocking performance and energy improvement opportunities. - Nagendra Dwarakanath Gulur; R. Manikantan; Mahesh Mehendale; R. Govindarajan (ICS, 2012)

Probabilistic Shared Cache Management (PriSM). - R. Manikantan; Kaushik Rajan; R. Govindarajan (ISCA, 2012)

On-chip memory architecture exploration framework for DSP processor-based embedded system on chip. - T. S. Rajesh Kumar; R. Govindarajan; C. P. Ravikumar (ACM Trans. Embed. Comput. Syst., 2012)

Parallel flow-sensitive pointer analysis by graph-rewriting. - Vaivaswatha Nagaraj; R. Govindarajan (PACT, 2013)

Improving GPGPU concurrency with elastic kernels. - Sreepathi Pai; Matthew J. Thazhuthaveetil; R. Govindarajan (ASPLOS, 2013)

Runtime dependence computation and execution of loops on heterogeneous systems. - Jayvant Anantpur; R. Govindarajan (CGO, 2013)

Fast Likelihood Computation in Speech Recognition using Matrices. - Mrugesh R. Gajjar; T. V. Sreenivas; R. Govindarajan (J. Signal Process. Syst., 2013)

Preemptive thread block scheduling with online structural runtime prediction for concurrent GPGPU kernels. - Sreepathi Pai; R. Govindarajan; Matthew J. Thazhuthaveetil (PACT, 2014)

Taming Control Divergence in GPUs through Control Flow Linearization. - Jayvant Anantpur; R. Govindarajan (CC, 2014)

Fluidic Kernels: Cooperative Execution of OpenCL Programs on Multiple Heterogeneous Devices. - Prasanna Pandit; R. Govindarajan (CGO, 2014)

Bi-Modal DRAM Cache: Improving Hit Rate, Hit Latency and Bandwidth. - Nagendra Dwarakanath Gulur; Mahesh Mehendale; R. Manikantan; R. Govindarajan (MICRO, 2014)

ANATOMY: an analytical model of memory system performance. - Nagendra Gulur; Mahesh Mehendale; Raman Manikantan; Ramaswamy Govindarajan (SIGMETRICS, 2014)

Compiler/Runtime Framework for Dynamic Dataflow Parallelization of Tiled Programs. - Martin Kong; Antoniu Pop; Louis-Noël Pouchet; R. Govindarajan; Albert Cohen 001; P. Sadayappan (ACM Trans. Archit. Code Optim., 2014)

Approximating flow-sensitive pointer analysis using frequent itemset mining. - Vaivaswatha Nagaraj; R. Govindarajan (CGO, 2015)

PRO: Progress Aware GPU Warp Scheduling Algorithm. - Jayvant Anantpur; R. Govindarajan (IPDPS, 2015)

A Comprehensive Analytical Performance Model of DRAM Caches. - Nagendra Dwarakanath Gulur; Mahesh Mehendale; Ramaswamy Govindarajan (ICPE, 2015)

Author Rebuttal to Rocha et al. "Comments on Minimizing Buffer Requirements under Rate-Optimal Schedule in Regular Dataflow Networks". - R. Govindarajan; Guang R. Gao (J. Signal Process. Syst., 2015)

MicroRefresh: Minimizing Refresh Overhead in DRAM Caches. - Nagendra Gulur; R. Govindarajan; Mahesh Mehendale (MEMSYS, 2016)

Taming warp divergence. - Jayvant Anantpur; R. Govindarajan (CGO, 2017)

RLWS: A Reinforcement Learning based GPU Warp Scheduler. - Jayvant Anantpur; Nagendra Dwarakanath Gulur; Shivaram Kalyanakrishnan; Shalabh Bhatnagar; R. Govindarajan (CoRR, 2017)

HAShCache: Heterogeneity-Aware Shared DRAMCache for Integrated Heterogeneous Systems. - Adarsh Patil 002; Ramaswamy Govindarajan (ACM Trans. Archit. Code Optim., 2017)

On odd harmonious labelling of even cycles with parallel chords and dragons with parallel chords. - V. Srividya; R. Govindarajan (Int. J. Comput. Aided Eng. Technol., 2020)

Treebeard: An Optimizing Compiler for Decision Tree Based ML Inference. - Ashwin Prasad; Sampath Rajendra; Kaushik Rajan; R. Govindarajan; Uday Bondhugula (MICRO, 2022)

Reduce, Reuse, and Adapt: Accelerating Graph Processing on GPUs. - Ullas A; Rupesh Nasre; R. Govindarajan (HiPC, 2023)

Tile Size and Loop Order Selection using Machine Learning for Multi-/Many-Core Architectures. - Shilpa Babalad; Shirish K. Shevade; Matthew Jacob Thazhuthaveetil; R. Govindarajan (ICS, 2024)

SilvanForge: A Schedule-Guided Retargetable Compiler for Decision Tree Inference. - Ashwin Prasad; Sampath Rajendra; Kaushik Rajan; R. Govindarajan; Uday Bondhugula (SOSP, 2024)

Performance Characterization and Optimizations of Traditional ML Applications. - Harsh Kumar; R. Govindarajan (CoRR, 2024)