A 100-MHz macropipelined VAX microprocessor. - Roy W. Badeau; R. Iris Bahar; Debra Bemstein; Larry L. Biro; William J. Bowhill; John F. Brown III; Michael A. Case; Ruben W. Castelino; Elizabeth M. Cooper; Maureen A. Delaney; David R. Deverell; John H. Edmondson; et al. (IEEE J. Solid State Circuits, 1992)

Timing Analysis of Combinational Circuits using ADD's. - R. Iris Bahar; Hyunwoo Cho; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (EDAC-ETC-EUROASIC, 1994)

An ADD-based algorithm for shortest path back-tracing of large graphs. - R. Iris Bahar; Gary D. Hachtel; Abelardo Pardo; Massimo Poncino; Fabio Somenzi (Great Lakes Symposium on VLSI, 1994)

A symbolic method to reduce power consumption of circuits containing false paths. - R. Iris Bahar; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (ICCAD, 1994)

Computing the Maximum Power Cycles of a Sequential Circuit. - Srilatha Manne; Abelardo Pardo; R. Iris Bahar; Gary D. Hachtel; Fabio Somenzi; Enrico Macii; Massimo Poncino (DAC, 1995)

Boolean techniques for low power driven re-synthesis. - R. Iris Bahar; Fabio Somenzi (ICCAD, 1995)

CMOS dynamic power estimation based on collapsible current source transistor modeling. - Abelardo Pardo; R. Iris Bahar; Srilatha Manne; Peter Feldmann; Gary D. Hachtel; Fabio Somenzi (ISLPD, 1995)

Symbolic computation of logic implications for technology-dependent low-power synthesis. - R. Iris Bahar; M. Burns; Gary D. Hachtel; Enrico Macii; H. Shin; Fabio Somenzi (ISLPED, 1996)

Algebraic Decision Diagrams and Their Applications. - R. Iris Bahar; Erica A. Frohm; Charles M. Gaona; Gary D. Hachtel; Enrico Macii; Abelardo Pardo; Fabio Somenzi (Formal Methods Syst. Des., 1997)

Symbolic timing analysis and resynthesis for low power of combinational circuits containing false paths. - R. Iris Bahar; Hyunwoo Cho; Gary D. Hachtel; Enrico Macii; Fabio Somenzi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997)

Power and performance tradeoffs using various caching strategies. - R. Iris Bahar; Gianluca Albera; Srilatha Manne (ISLPED, 1998)

The Non-Critical Buffer: Using Load Latency Tolerance to Improve Data Cache Efficiency. - Brian R. Fisk; R. Iris Bahar (ICCD, 1999)

A comparison of software code reordering and victim buffers. - R. Iris Bahar; Brad Calder; Dirk Grunwald (SIGARCH Comput. Archit. News, 1999)

Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors. - Roberto Maro; Yu Bai 001; R. Iris Bahar (PACS, 2000)

Power optimization of technology-dependent circuits based on symbolic computation of logic implications. - R. Iris Bahar; Ernest T. Lampe; Enrico Macii (ACM Trans. Design Autom. Electr. Syst., 2000)

Power and energy reduction via pipeline balancing. - R. Iris Bahar; Srilatha Manne (ISCA, 2001)

Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. - Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (IWLS, 2002)

Combining Software and Hardware Monitoring for Improved Power and Performance Tuning. - Eric Chi; A. Michael Salem; R. Iris Bahar; Richard S. Weiss (Interaction between Compilers and Computer Architectures, 2003)

Power-aware issue queue design for speculative instructions. - Tali Moreshet; R. Iris Bahar (DAC, 2003)

A Probabilistic-Based Design Methodology for Nanoscale Computation. - R. Iris Bahar; Joseph L. Mundy; Jie Chen 002 (ICCAD, 2003)

Symbolic Failure Analysis of Custom Circuits due to Excessive Leakage Current. - Hui-Yuan Song; S. Bohidar; R. Iris Bahar; Joel Grodstein (ICCD, 2003)

A Dynamically Reconfigurable Mixed In-Order/Out-of-Order Issue Queue for Power-Aware Microprocessors. - Yu Bai 001; R. Iris Bahar (ISVLSI, 2003)

RESTA: a robust and extendable symbolic timing analysis tool. - Kundan Nepal; Hui-Yuan Song; R. Iris Bahar; Joel Grodstein (ACM Great Lakes Symposium on VLSI, 2004)

Reducing Issue Queue Power for Multimedia Applications using a Feedback Control Algorithm. - Yu Bai 001; R. Iris Bahar (ICCD, 2004)

Fetch Halting on Critical Load Misses. - Nikil Mehta; Brian Singer; R. Iris Bahar; Michael Leuchtenburg; Richard S. Weiss (ICCD, 2004)

A low-power in-order/out-of-order issue queue. - Yu Bai 001; R. Iris Bahar (ACM Trans. Archit. Code Optim., 2004)

Effects of speculation on performance and issue queue design. - Tali Moreshet; R. Iris Bahar (IEEE Trans. Very Large Scale Integr. Syst., 2004)

Designing logic circuits for probabilistic computation in the presence of noise. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DAC, 2005)

Energy reduction in multiprocessor systems using transactional memory. - Tali Moreshet; R. Iris Bahar; Maurice Herlihy (ISLPED, 2005)

Guest Editors' Introduction: Challenges for Reliable Design at the Nanoscale. - R. Iris Bahar; Mehdi Baradaran Tahoori; Sandeep K. Shukla; Fabrizio Lombardi (IEEE Des. Test Comput., 2005)

Symbolic failure analysis of complex CMOS circuits due to excessive leakage current and charge sharing. - R. Iris Bahar; Hui-Yuan Song; Kundan Nepal; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors. - Vladimir Stojanovic; R. Iris Bahar; Jennifer Dworak; Richard Weiss 001 (DAC, 2006)

Designing MRF based error correcting circuits for memory elements. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2006)

Optimizing noise-immune nanoscale circuits using principles of Markov random fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2006)

Trends and Future Directions in Nano Structure Based Computing and Fabrication. - R. Iris Bahar (ICCD, 2006)

Energy implications of multiprocessor synchronization. - Tali Moreshet; R. Iris Bahar; Maurice Herlihy (SPAA, 2006)

MRF Reinforcer: A Probabilistic Element for Space Redundancy in Nanoscale Circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (IEEE Micro, 2006)

Timing analysis for full-custom circuits using symbolic DC formulations. - Hui-Yuan Song; Kundan Nepal; R. Iris Bahar; Joel Grodstein (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Interactive presentation: Techniques for designing noise-tolerant multi-level combinational circuits. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (DATE, 2007)

Accurate timing analysis using SAT and pattern-dependent delay models. - Desta Tadesse; D. Sheffield; E. Lenge; R. Iris Bahar; Joel Grodstein (DATE, 2007)

Strategies for improving the parametric yield and profits of 3D ICs. - Cesare Ferri; Sherief Reda; R. Iris Bahar (ICCAD, 2007)

Thermally-induced soft errors in nanoscale CMOS circuits. - Hua Li; Joseph L. Mundy; William R. Patterson; Dimitrios Kazazis; Alexander Zaslavsky; R. Iris Bahar (NANOARCH, 2007)

Architectures for Silicon Nanoelectronics and Beyond. - R. Iris Bahar; Dan W. Hammerstrom; Justin E. Harlow III; William H. Joyner Jr.; Clifford Lau; Diana Marculescu; Alex Orailoglu; Massoud Pedram (Computer, 2007)

Designing Nanoscale Logic Circuits Based on Markov Random Fields. - Kundan Nepal; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (J. Electron. Test., 2007)

A hardware/software framework for supporting transactional memory in a MPSoC environment. - Cesare Ferri; Tali Moreshet; R. Iris Bahar; Luca Benini; Maurice Herlihy (SIGARCH Comput. Archit. News, 2007)

Temperature-insensitive synthesis using multi-vt libraries. - Andrea Calimera; Enrico Macii; Massimo Poncino; R. Iris Bahar (ACM Great Lakes Symposium on VLSI, 2008)

Energy efficient synchronization techniques for embedded architectures. - Cesare Ferri; Amber Viescas; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (ACM Great Lakes Symposium on VLSI, 2008)

Reducing leakage power by accounting for temperature inversion dependence in dual-Vt synthesized circuits. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (ISLPED, 2008)

Using Implications for Online Error Detection. - Kundan Nepal; Nuno Alves; Jennifer Dworak; R. Iris Bahar (ITC, 2008)

Fast Measurement of the "Non-Deterministic Zone" in Microprocessor Debug Using Maximum Likelihood Estimation. - Desta Tadesse; R. Iris Bahar; Joel Grodstein (VTS, 2008)

Parametric yield management for 3D ICs: Models and strategies for improvement. - Cesare Ferri; Sherief Reda; R. Iris Bahar (ACM J. Emerg. Technol. Comput. Syst., 2008)

Thermal-Aware Design Techniques for Nanometer CMOS Circuits. - Andrea Calimera; Karthik Duraisami; Ashoka Visweswara Sathanur; Prassanna Sithambaram; R. Iris Bahar; Alberto Macii; Enrico Macii; Massimo Poncino (J. Low Power Electron., 2008)

Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies. - R. Iris Bahar; Krishnendu Chakrabarty (ACM Trans. Design Autom. Electr. Syst., 2008)

Detecting errors using multi-cycle invariance information. - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (DATE, 2009)

High-performance, cost-effective heterogeneous 3D FPGA architectures. - Roto Le; Sherief Reda; R. Iris Bahar (FPGA, 2009)

Energy-optimal synchronization primitives for single-chip multi-processors. - Cesare Ferri; R. Iris Bahar; Mirko Loghi; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2009)

Compacting test vector sets via strategic use of implications. - Nuno Alves; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (ICCAD, 2009)

Reducing the leakage and timing variability of 2D ICcs using 3D ICs. - Sherief Reda; Aung Si; R. Iris Bahar (ISLPED, 2009)

AutoRex: An automated post-silicon clock tuning tool. - Desta Tadesse; Joel Grodstein; R. Iris Bahar (ITC, 2009)

Introduction to special section: Best of NANOARCH 2008. - R. Iris Bahar (ACM J. Emerg. Technol. Comput. Syst., 2009)

Improving the testability and reliability of sequential circuits with invariant logic. - Nuno Alves; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (ACM Great Lakes Symposium on VLSI, 2010)

Numerical queue solution of thermal noise-induced soft errors in subthreshold CMOS devices. - Pooya Jannaty; Florian C. Sabou; R. Iris Bahar; Joseph L. Mundy; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2010)

Energy and Throughput Efficient Transactional Memory for Embedded Multicore Systems. - Cesare Ferri; Samantha Wood 001; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (HiPEAC, 2010)

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems. - Cesare Ferri; Samantha Wood 001; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (J. Parallel Distributed Comput., 2010)

Dual-Vt assignment policies in ITD-aware synthesis. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (Microelectron. J., 2010)

A Cost Effective Approach for Online Error Detection Using Invariant Relationships. - Nuno Alves; Alison Buben; Kundan Nepal; Jennifer Dworak; R. Iris Bahar (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Temperature-Insensitive Dual- Vth Synthesis for Nanometer CMOS Technologies Under Inverse Temperature Dependence. - Andrea Calimera; R. Iris Bahar; Enrico Macii; Massimo Poncino (IEEE Trans. Very Large Scale Integr. Syst., 2010)

SoC-TM: integrated HW/SW support for transactional memory programming on embedded MPSoCs. - Cesare Ferri; Andrea Marongiu; Benjamin Lipton; R. Iris Bahar; Tali Moreshet; Luca Benini; Maurice Herlihy (CODES+ISSS, 2011)

Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis. - Nuno Alves; Yiwen Shi; Nicholas Imbriglia; Jennifer Dworak; Kundan Nepal; R. Iris Bahar (ETS, 2011)

NBTI-aware data allocation strategies for scratchpad memory based embedded systems. - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (LATW, 2011)

A novel parallel Tier-1 coder for JPEG2000 using GPUs. - Roto Le; R. Iris Bahar; Joseph L. Mundy (SASP, 2011)

Enhancing online error detection through area-efficient multi-site implications. - Nuno Alves; Yiwen Shi; Jennifer Dworak; R. Iris Bahar; Kundan Nepal (VTS, 2011)

Test Vector Generation for Post-Silicon Delay Testing Using SAT-Based Decision Problems. - Desta Tadesse; R. Iris Bahar; Joel Grodstein (J. Electron. Test., 2011)

High Performance Parallel JPEG2000 Streaming Decoder Using GPGPU-CPU Heterogeneous System. - Roto Le; Joseph L. Mundy; R. Iris Bahar (ASAP, 2012)

Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. - Kumud Nepal; Onur Ulusel; R. Iris Bahar; Sherief Reda (FCCM, 2012)

A noise-immune sub-threshold circuit design based on selective use of Schmitt-trigger logic. - Marco Donato; Fabio Cremona; Warren Jin 002; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky; Joseph L. Mundy (ACM Great Lakes Symposium on VLSI, 2012)

NBTI-Aware Data Allocation Strategies for Scratchpad Based Embedded Systems. - Cesare Ferri; Dimitra Papagiannopoulou; R. Iris Bahar; Andrea Calimera (J. Electron. Test., 2012)

Using implications to choose tests through suspect fault identification. - Jennifer Dworak; Kundan Nepal; Nuno Alves; Yiwen Shi; Nicholas Imbriglia; R. Iris Bahar (ACM Trans. Design Autom. Electr. Syst., 2012)

Built-in Self-Repair in a 3D die stack using programmable logic. - Kundan Nepal; Xi Shen; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (DFTS, 2013)

Transparent and energy-efficient speculation on NUMA architectures for embedded MPSoCs. - Dimitra Papagiannopoulou; R. Iris Bahar; Tali Moreshet; Maurice Herlihy; Andrea Marongiu; Luca Benini (MES, 2013)

Flexible data allocation for scratch-pad memories to reduce NBTI effects. - Dimitra Papagiannopoulou; Patipan Prasertsom; R. Iris Bahar (ISQED, 2013)

"Scaling" the impact of EDA education Preliminary findings from the CCC workshop series on extreme scale design automation. - R. Iris Bahar; Alex K. Jones; Srinivas Katkoori; Patrick H. Madden; Diana Marculescu; Igor L. Markov (MSE, 2013)

ABACUS: A technique for automated behavioral synthesis of approximate computing circuits. - Kumud Nepal; Yueting Li; R. Iris Bahar; Sherief Reda (DATE, 2014)

Speculative synchronization for coherence-free embedded NUMA architectures. - Dimitra Papagiannopoulou; Tali Moreshet; Andrea Marongiu; Luca Benini; Maurice Herlihy; R. Iris Bahar (ICSAMOS, 2014)

Fast Design Exploration for Performance, Power and Accuracy Tradeoffs in FPGA-Based Accelerators. - Onur Ulusel; Kumud Nepal; R. Iris Bahar; Sherief Reda (ACM Trans. Reconfigurable Technol. Syst., 2014)

A Simulation Framework for Analyzing Transient Effects Due to Thermal Noise in Sub-Threshold Circuits. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (ACM Great Lakes Symposium on VLSI, 2015)

Playing with Fire: Transactional Memory Revisited for Error-Resilient and Energy-Efficient MPSoC Execution. - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Luca Benini; Maurice Herlihy; R. Iris Bahar (ACM Great Lakes Symposium on VLSI, 2015)

DRUM: A Dynamic Range Unbiased Multiplier for Approximate Applications. - Soheil Hashemi; R. Iris Bahar; Sherief Reda (ICCAD, 2015)

Message from the program co-chairs. - Jun Wang 001; Iris Bahar (NAS, 2015)

Repairing a 3-D Die-Stack Using Available Programmable Logic. - Kundan Nepal; Soha Alhelaly; Jennifer Dworak; R. Iris Bahar; Theodore W. Manikas; Ping Guikundan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Energy-Efficient and High-Performance Lock Speculation Hardware for Embedded Multicore Systems. - Dimitra Papagiannopoulou; Giuseppe Capodanno; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (ACM Trans. Embed. Comput. Syst., 2015)

Introduction to the Special Issue on Reliable, Resilient, and Robust Design of Circuits and Systems. - R. Iris Bahar; Alex K. Jones; Yuan Xie 001 (ACM Trans. Design Autom. Electr. Syst., 2015)

Thrifty-malloc: A HW/SW codesign for the dynamic management of hardware transactional memory in embedded multicore systems. - Thomas Carle; Dimitra Papagiannopoulou; Tali Moreshet; Andrea Marongiu; Maurice Herlihy; R. Iris Bahar (CASES, 2016)

Runtime configurable deep neural networks for energy-accuracy trade-off. - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (CODES+ISSS, 2016)

A fast simulator for the analysis of sub-threshold thermal noise transients. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (DAC, 2016)

A low-power dynamic divider for approximate applications. - Soheil Hashemi; R. Iris Bahar; Sherief Reda (DAC, 2016)

Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. - Onur Ulusel; Christopher B. Picardo; Christopher B. Harris; Sherief Reda; R. Iris Bahar (FPL, 2016)

Design of Error-Resilient Logic Gates with Reinforcement Using Implications. - Xijing Han; Marco Donato; R. Iris Bahar; Alexander Zaslavsky; William R. Patterson (ACM Great Lakes Symposium on VLSI, 2016)

Using Existing Reconfigurable Logic in 3D Die Stacks for Test. - Fanchen Zhang; Yi Sun; Xi Shen; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; Ping Gui; R. Iris Bahar; Al Crouch; John C. Potter (NATW, 2016)

Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. - Hokchhay Tann; Soheil Hashemi; R. Iris Bahar; Sherief Reda (DAC, 2017)

Understanding the impact of precision quantization on the accuracy and energy of neural networks. - Soheil Hashemi; Nicholas Anthony; Hokchhay Tann; R. Iris Bahar; Sherief Reda (DATE, 2017)

Evaluating critical bits in arithmetic operations due to timing violations. - Sungseob Whang; Tymani Rachford; Dimitra Papagiannopoulou; Tali Moreshet; R. Iris Bahar (HPEC, 2017)

Comprehensive comparison of gradient-based cross-spectral stereo matching generated disparity maps. - Christopher B. Picardo; Justin G. R. Delva; R. Iris Bahar (MWSCAS, 2017)

A Research Tool for the Power and Performance Analysis of Sensor-Based Mobile Robots. - Christopher B. Harris; R. Iris Bahar (NGCAS, 2017)

Edge-TM: Exploiting Transactional Memory for Error Tolerance and Energy Efficiency. - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (ACM Trans. Embed. Comput. Syst., 2017)

Robust object estimation using generative-discriminative inference for secure robotics applications. - Yanqi Liu; Alessandro Costantini; R. Iris Bahar; Zhiqiang Sui; Zhefan Ye; Shiyang Lu; Odest Chadwicke Jenkins (ICCAD, 2018)

Conference Reports: Report on the 2017 International Conference on Computer-Aided Design (ICCAD). - Sri Parameswaran; R. Iris Bahar; David Z. Pan (IEEE Des. Test, 2018)

Hardware Transactional Memory Exploration in Coherence-Free Many-Core Architectures. - Dimitra Papagiannopoulou; Andrea Marongiu; Tali Moreshet; Luca Benini; Maurice Herlihy; R. Iris Bahar (Int. J. Parallel Program., 2018)

Towards the Simulation Based Design and Validation of Mobile Robotic Cyber-Physical Systems. - Christopher B. Harris; R. Iris Bahar (J. Low Power Electron., 2018)

A Sub-Threshold Noise Transient Simulator Based on Integrated Random Telegraph and Thermal Noise Modeling. - Marco Donato; R. Iris Bahar; William R. Patterson; Alexander Zaslavsky (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

IgnoreTM: Opportunistically Ignoring Timing Violations for Energy Savings using HTM. - Dimitra Papagiannopoulou; Sungseob Whang; Tali Moreshet; R. Iris Bahar (DATE, 2019)

Energy-efficient and Sustainable Computing across the Hardware/Software Stack. - Iris Bahar (IGSC, 2019)

Test Architecture for Fine Grained Capture Power Reduction. - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Matan Segal; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (ICECS, 2019)

Barrier Synchronization vs. Voltage Noise: A Quantitative Analysis. - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IISWC, 2019)

GRIP: Generative Robust Inference and Perception for Semantic Robot Manipulation in Adversarial Environments. - Xiaotong Chen; Rui Chen; Zhiqiang Sui; Zhefan Ye; Yanqi Liu; R. Iris Bahar; Odest Chadwicke Jenkins (IROS, 2019)

Attacking memory-hard scrypt with near-data-processing. - Jiwon Choe; Tali Moreshet; R. Iris Bahar; Maurice Herlihy (MEMSYS, 2019)

Concurrent Data Structures with Near-Data-Processing: an Architecture-Aware Implementation. - Jiwon Choe; Amy Huang; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (SPAA, 2019)

Special Session: Does Approximation Make Testing Harder (or Easier)? - R. Iris Bahar; Ulya R. Karpuzcu; Sasa Misailovic (VTS, 2019)

Conference Reports: Recap of the 37th Edition of the International Conference on Computer-Aided Design (ICCAD 2018). - R. Iris Bahar (IEEE Des. Test, 2019)

Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. - Yi Sun; Fanchen Zhang; Hui Jiang; Kundan Nepal; Jennifer Dworak; Theodore W. Manikas; R. Iris Bahar (J. Electron. Test., 2019)

Automated High-Level Generation of Low-Power Approximate Computing Circuits. - Kumud Nepal; Soheil Hashemi; Hokchhay Tann; R. Iris Bahar; Sherief Reda (IEEE Trans. Emerg. Top. Comput., 2019)

Hardware Acceleration of Monte-Carlo Sampling for Energy Efficient Robust Robot Manipulation. - Yanqi Liu; Giuseppe Calderoni; Ruth Iris Bahar (FPL, 2020)

Hardware Acceleration of Robot Scene Perception Algorithms. - Yanqi Liu; Can Eren Derman; Giuseppe Calderoni; R. Iris Bahar (ICCAD, 2020)

Voltage Noise Mitigation With Barrier Approximation. - Zamshed I. Chowdhury; S. Karen Khatamifard; Zhaoyong Zheng; Tali Moreshet; R. Iris Bahar; Ulya R. Karpuzcu (IEEE Comput. Archit. Lett., 2020)

Workshops on Extreme Scale Design Automation (ESDA) Challenges and Opportunities for 2025 and Beyond. - R. Iris Bahar; Alex K. Jones; Srinivas Katkoori; Patrick H. Madden; Diana Marculescu; Igor L. Markov (CoRR, 2020)

Low Power Shift and Capture through ATPG-Configured Embedded Enable Capture Bits. - Yi Sun; Hui Jiang; Lakshmi Ramakrishnan; Jennifer Dworak; Kundan Nepal; Theodore W. Manikas; R. Iris Bahar (ITC, 2021)

Using Human-Guided Causal Knowledge for More Generalized Robot Task Planning. - Semir Tatlidil; Yanqi Liu; Emily Sheetz; R. Iris Bahar; Steven A. Sloman (CoRR, 2021)

Hardware Acceleration of Nonparametric Belief Propagation for Efficient Robot Manipulation. - Yanqi Liu; Anthony Opipari; Théo Guérin; Ruth Iris Bahar (FPGA, 2022)

Towards Hardware Accelerated Garbage Collection with Near-Memory Processing. - Samuel Thomas; Jiwon Choe; Ofir Gordon; Erez Petrank; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (HPEC, 2022)

A Reconfigurable Hardware Library for Robot Scene Perception. - Yanqi Liu; Anthony Opipari; Odest Chadwicke Jenkins; R. Iris Bahar (ICCAD, 2022)

EDAML 2022 Invited Speaker 3: Scalable ML Architectures for Real-time Energy-efficient Computing. - R. Iris Bahar (IPDPS Workshops, 2022)

Eliminating Micro-Architectural Side-Channel Attacks using Near Memory Processing. - Casey Nelson; Joseph Izraelevitz; R. Iris Bahar; Tamara Silbergleit Lehman (SEED, 2022)

HybriDS: Cache-Conscious Concurrent Data Structures for Near-Memory Processing Architectures. - Jiwon Choe; Andrew Crotty; Tali Moreshet; Maurice Herlihy; R. Iris Bahar (SPAA, 2022)

LipoPose: Adapting Cellpose to Lipid Nanoparticle Segmentation. - Semanti Basu; Peter Bajcsy; Thomas E. Cleveland IV; Manuel J. Carrasco; R. Iris Bahar (BIOIMAGING, 2023)

A Midsummer Night's Tree: Efficient and High Performance Secure SCM. - Samuel Thomas; Kidus Workneh; Jac McCarty; Joseph Izraelevitz; Tamara Lehman; R. Iris Bahar (ASPLOS (3), 2024)

Invited: Using Causal Information to Enable More Efficient Robot Operation. - Semanti Basu; Semir Tatlidil; Moon Hwan Kim; Steven A. Sloman; R. Iris Bahar (DAC, 2024)

Baobab Merkle Tree for Efficient Secure Memory. - Samuel Thomas; Kidus Workneh; Ange-Thierry Ishimwe; Zack McKevitt; Phaedra S. Curlin; R. Iris Bahar; Joseph Izraelevitz; Tamara Lehman (IEEE Comput. Archit. Lett., 2024)