FPGA design and implementation of truncated multipliers using bypassing technique. - S. Balamurugan 001; Balakumaran Srirangaswamy; R. Marimuthu 001; Partha Sharathi Mallick (ICACCI, 2012)

Design of low power fixed-width multiplier with row bypassing. - S. Balamurugan 001; Sneha Ghosh; Atul; Balakumaran Srirangaswamy; R. Marimuthu 001; Partha Sharathi Mallick (IEICE Electron. Express, 2012)

Design and Analysis of Multiplier Using Approximate 15-4 Compressor. - R. Marimuthu 001; Y. Elsie Rezinold; Partha Sharathi Mallick (IEEE Access, 2017)

Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD. - Saurabh Kumar; R. Marimuthu 001; S. Balamurugan 001 (SocProS (2), 2018)

Realization of 2-D DCT Using Adder Compressor. - Raunak R. Lahoti; Shantanu Agarwal; S. Balamurugan 001; R. Marimuthu 001 (SocProS (2), 2018)

Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic. - Shantanu Agarwal; G. Harish; S. Balamurugan 001; R. Marimuthu 001 (VDAT, 2018)

Design of 5-3 multicolumn compressor for high performance multiplier. - R. Marimuthu 001; S. Balamurugan 001; Partha Sharathi Mallick (Int. J. Comput. Aided Eng. Technol., 2018)

Integration of AC/DC With Multi Input Mode Selection Converter for Fast Charging of Battery in Electric Vehicles. - V. Ramya; R. Marimuthu 001 (IEEE Access, 2024)

Conglomeration of deep neural network and quantum learning for object detection: Status quo review. - Piyush Kumar Sinha; R. Marimuthu 001 (Knowl. Based Syst., 2024)

Quantum Algorithms' Approach: A Case Study on Bladeless Wind Turbine and Solar Panel. - Piyush Kumar Sinha; R. Marimuthu 001 (IEEE Access, 2025)