Device and Circuit Design Challenges in the Digital Subthreshold Region for Ultralow-Power Applications. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (VLSI Design, 2009)

Comparison of nano-scale complementary metal-oxide semiconductor and 3T-4T double gate fin-shaped field-effect transistors for robust and energy-efficient subthreshold logic. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (IET Circuits Devices Syst., 2010)

Robust and Ultra Low Power Subthreshold Logic Circuits with Symmetric, Asymmetric, 3T, 4T DGFinFETs. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (J. Low Power Electron., 2010)

Robustness comparison of DG FinFETs with symmetric, asymmetric, tied and independent gate options with circuit co-design for ultra low power subthreshold logic. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (Microelectron. J., 2010)

Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. - Ramesh Vaddi; Sudeb Dasgupta; R. P. Agarwal (ISVLSI, 2011)

An Efficient Software Watermark by Equation Reordering and FDOS. - B. K. Sharma; R. P. Agarwal; Raghuraj Singh (SocProS (2), 2011)

Analytical modeling of subthreshold current and subthreshold swing of an underlap DGMOSFET with tied-independent gate and symmetric-asymmetric options. - Ramesh Vaddi; R. P. Agarwal; Sudeb Dasgupta (Microelectron. J., 2011)

Numerical approximation of fractional variational problems with several dependent variables using Jacobi poly-fractonomials. - Divyansh Pandey; Rajesh Kumar Pandey; R. P. Agarwal (Math. Comput. Simul., 2023)