Experimental Study on Substrate Noise Effects of a Pulsed Clocking Scheme on PLL Performance. - R. R. Manikandan; Bharadwaj Amrutur (IEEE Trans. Circuits Syst. II Express Briefs, 2013)

Design and modeling of high-Q variable width and spacing, planar and 3-D stacked spiral inductors. - R. R. Manikandan; Venkata Narayana Rao Vanukuru; Anjan Chakravorty; Bharadwaj S. Amrutur (VDAT, 2014)

A zero charge-pump mismatch current tracking loop for reference spur reduction in PLLs. - R. R. Manikandan; Bharadwaj S. Amrutur (Microelectron. J., 2015)

A Digital Frequency Multiplication Technique for Energy Efficient Transmitters. - R. R. Manikandan; Abhishek Kumar 007; Bharadwaj Amrutur (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A High Performance Switchable Multiband Inductor Structure for LC-VCOs. - R. R. Manikandan; Venkata Narayana Rao Vanukuru (VLSID, 2017)

A 1.2 pJ/cycle KHz Timer Circuit for Heavily Duty-Cycled Systems. - R. R. Manikandan; Vipul Kumar Singhal 001; Rajat Chauhan; Vinod Menezes; Mahesh Mehendale (VLSID, 2018)

150nA IQ, Quad Input - Quad Output, Intelligent Integrated Power Management for IoT Applications. - Vipul Singhal 001; Rajat Chauhan; Vinod Menezes; R. R. Manikandan; Raveesh Magod; Mahesh Mehendale; Anantha P. Chandrakasan (VLSID, 2021)