SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. - R. Rajaraman; Jungsub Kim; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin (VLSI Design, 2006)

Variation Impact on SER of Combinational Circuits. - Krishnan Ramakrishnan; R. Rajaraman; Sivaprakasam Suresh; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin (ISQED, 2007)

Soft Error Rate Analysis for Combinational Logic Using An Accurate Electrical Masking Model. - Feng Wang 004; Yuan Xie 001; R. Rajaraman; Balaji Vaidyanathan (VLSI Design, 2007)

Hierarchical Soft Error Estimation Tool (HSEET). - Krishnan Ramakrishnan; R. Rajaraman; Narayanan Vijaykrishnan; Yuan Xie 001; Mary Jane Irwin; Kenan Unlu (ISQED, 2008)