Method to evaluate off-state breakdown in scaled Tri-gate technologies. - D. Nminibapiel; K. Joshi; R. Ramamurthy; L. Pantisano; Inanc Meric; Stephen Ramey (IRPS, 2022)

A detailed comparison of various off-state breakdown methodologies for scaled Tri-gate technologies. - K. Joshi; D. Nminibapiel; M. Ghoneim; D. Ali; R. Ramamurthy; L. Pantisano; Inanc Meric; Stephen Ramey (IRPS, 2023)

Novel Cell Architectures with Back-side Transistor Contacts for Scaling and Performance. - Mauro J. Kobrinsky; J. D. Silva; E. Mannebach; S. Mills; M. Abd El Qader; O. Adebayo; N. Arkali Radhakrishna; M. Beasley; J. Chawla; S. Chugh; A. Dasgupta; U. Desai; et al. (VLSI Technology and Circuits, 2023)

Record Performance in GAA 2D NMOS and PMOS Using Monolayer MoS2 and WSe2 with Scaled Contact and Gate Length. - W. Mortelmans; P. Buragohain; C. Rogan; A. Kitamura; C. J. Dorow; K. P. O'Brien; R. Ramamurthy; J. Lux; T. Zhong; S. Harlson; E. Gillispie; T. Wilson; et al. (VLSI Technology and Circuits, 2024)