Low power energy efficient pipelined multiply-accumulate architecture. - R. Sakthivel 002; K. Sravanthi; Harish M. Kittur (ICACCI, 2012)

Design of dynamically reconfigurable fully optimized low power FFT architecture for MC-CDMA receiver. - R. Sakthivel 002; Harish M. Kittur (IEICE Electron. Express, 2013)

Energy Efficient Low Area Error Tolerant Adder with Higher Accuracy. - R. Sakthivel 002; Harish M. Kittur (Circuits Syst. Signal Process., 2014)

Low power high throughput reconfigurable stream cipher hardware VLSI architectures. - R. Sakthivel 002; M. Vanitha; Harish M. Kittur (Int. J. Inf. Comput. Secur., 2014)

Nonlinear System Modelling Using Programmable Hardware for Soft Computing Applications. - M. Vanitha; R. Sakthivel 002; Mangayarkarasi Ramaiah; Suvarcha Sharma (SocProS (2), 2018)

High Performance GCM Architecture for the Security of High Speed Network. - Vanitha Mohanraj; Ramachandran Sakthivel; Anand Paul 001; Seungmin Rho (Int. J. Parallel Program., 2018)

Schmitt trigger-based single-ended 7T SRAM cell for Internet of Things (IoT) applications. - Kishore Sanapala; Ramachandran Sakthivel; Sang-Soo Yeo (J. Supercomput., 2018)

Ultra-low-voltage GDI-based hybrid full adder design for area and energy-efficient computing systems. - Kishore Sanapala; Ramachandran Sakthivel (IET Circuits Devices Syst., 2019)

High-performance ECC processor architecture design for IoT security applications. - Thirumalesu Kudithi; R. Sakthivel 002 (J. Supercomput., 2019)

Superior Implementation of Accelerated QR Decomposition for Ultrasound Imaging. - Sreejeesh S. G.; R. Sakthivel 002; Jayaraj U. Kidav (IEEE Access, 2020)

An efficient hardware implementation of the elliptic curve cryptographic processor over prime field, . - Thirumalesu Kudithi; R. Sakthivel 002 (Int. J. Circuit Theory Appl., 2020)

Design of Artificial Neuron Network with Synapse Utilizing Hybrid CMOS Transistors with Memristor for Low Power Applications. - V. Keerthy Rai; R. Sakthivel 002 (J. Circuits Syst. Comput., 2020)

VLSI System Architecture Optimization for DLMS Adaptive Filter using PPG based Multiplier. - Ramachandran Sakthivel; Premson Yohannan (Int. J. Syst. Syst. Eng., 2021)

Neuron Network with a Synapse of CMOS transistor and Anti-Parallel Memristors for Low power Implementations. - V. Keerthy Rai; R. Sakthivel 002 (J. Circuits Syst. Comput., 2022)

Mathematical and Circuit Level Analysis Interpretation and Recommendations on Neuron Models. - I. Munavar Sheriff; R. Sakthivel 002 (J. Circuits Syst. Comput., 2022)

Enhancement of Convolutional Neural Network Hardware Accelerators Efficiency Using Sparsity Optimization Framework. - Hemalatha Kurapati; Ramachandran Sakthivel (IEEE Access, 2024)

The Artificial Neuron: Built From Nanosheet Transistors to Achieve Ultra Low Power Consumption. - I. Munavar Sheriff; R. Sakthivel 002 (IEEE Access, 2024)

Generalized Bio-Plausible Neuron Model with Refractoriness, Frequency Adaptation and Dynamic Threshold. - I. Munavar Sheriff; R. Sakthivel 002 (J. Circuits Syst. Comput., 2024)

Multi-Parameter Comparative Study of Selective In-Memory Computing Processor Architectures for Performance Optimization in Accelerated Edge Computing. - V. Mohith; Shekhar Suman Borah; Prabha Sundaravadivel; R. Sakthivel 002 (ACM Great Lakes Symposium on VLSI, 2025)